Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology - VLSI Design and Test - page 193

6 Conclusion

We proposed a convex optimization model based on logical effort theory, extended to
model energy and delay, to give the optimum energy-delay trade-off through gate
sizing. The proposed model expresses switching energy of CMOS gates which reduc-
es the mathematical complexity and gives a good insight about a circuit performance.
The validation of the above model can be done either by solving mathematically and
then simulating or using MATLAB programming.

Acknowledgments. The authors are grateful to the lab facilities (Oysters Lab) of
Department of Electrical & Electronics Engineering at Birla Institute of Technology
& Science (BITS), Pilani where the work has been carried out.

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