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Fig. 3. Graph between Delay and electrical effort
We calibrated ˄ by measuring the delay of a logic gate as a function of delay and
electrical effort and fitting straight line to the results. The slope of the above curve
gives the ˄ for particular technology that is found to be equal to 1.92ps.The straight
line intersect the h=0 axis at d= ˄ p inv . Thus, the value of p inv is found to be 2.1019.
Validation for the above values were done by calculating the value of delay
theoretically for h=4, which comes out to be 11.715ps. At h=4, the simulated value
is 11.815ps from fig.3. The percentage error is less than 1% for the above calculated
values. Thus, from the above result, we finalized that the theoretical delay and
practical delays are matched for an inverter.
2.2
Gate Sizing for Delay Minimization
Now, an inverter chain having 7 stages with load capacitance of 100fF is considered.
The delay calculated without sizing the chain of inverter, by considering all inverter
dimensions equal for all stages, was found to be 198.16ps.
Now, resizing the chain of inverters for minimum delay the logical effort method
is used as in [3] and the widths of all the transistors are calculated for the load
capacitance of 100fF.
After resizing the gates of inverter stages using logical effort technique, the delay
of the inverter chain was found to be 116.044ps. Validation of this is done by simulat-
ing the inverter chain, for which the delay was found to be 113.9ps. The percentage
error is less than 2% for the above calculated values. Thus, from the above result we
finalized that the theoretical delay and practical delays are matched for an inverter
chain.
3
Power Dependence on Logical Effort
To determine the dependence of power on the logical effort parameter 'g' we used
two different inverter configurations, one having single NMOS and PMOS transistors
and another having two NMOS and one PMOS transistors, to vary input capacitance
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