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Table 1. Input Capacitances (C in ) of inverter in different region of operations. All
Capacitances are in femtofarad (fF).
S.No.
PMOS
NMOS
C gsn
gdn
gbn
C gbp
C in,total
C gsp
gdp
1
Linear
Cutoff
0
0
1.38
0
5.18
1.26
2.4
2
Sat.
Linear
0.69
1.30
0
1.69
0
0
3.69
3
Sat.
Sat.
2.07
0
0
0
2.60
1.69
0
4
Linear
Sat.
2.07
0
0
0
4.72
1.26
2.4
5
Cutoff
Linear
0.69
1.30
0
0
0
1.26
3.33
Finally, the theoretical value of the input capacitance, C in is calculated by taking
average of all input capacitances found in different regions of operation and is found
to be 3.923 fF.
Now, in order to validate the value of input capacitances found theoretically, simu-
lation is carried out using Spectre in cadence environment in UMC 90nm CMOS
technology and the values found are given in the table 2.
Table 2. Simulated CMOS inverter junction capacitances for different gate voltages using
Spectre in cadence environment in UMC 90nm CMOS technology
V G
C gsn (fF)
2C gdn (fF)
C gsp (fF)
2C gdp (fF)
C in,total (fF)
0
0.376
0.667
2.038
1.261
4.33
0.1
0.425
0.680
1.970
1.265
4.341
0.2
0.511
0.742
1.755
1.270
4.278
0.3
0.615
0.736
1.510
1.277
4.138
0.4
0.685
0.730
1.311
1.280
4.004
0.5
0.770
0.728
1.111
1.283
3.888
0.6
0.851
0.727
1.000
1.286
3.855
0.7
0.950
0.725
0.770
1.290
3.753
0.8
1.120
0.724
0.740
1.292
3.876
0.9
1.157
0.723
0.670
1.297
3.824
1.0
1.172
0.722
0.630
1.30
3.824
Taking the average of the simulated value, the input capacitance comes out to be
4.077fF. Thus, the theoretical value calculated is approximately same as simulated
value. To calculate delay for an inverter we require the value of ˄ and parasitic
capacitance, p inv . Thus, the delay of an inverter is calculated at different loads is
shown in fig. 3.
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