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The energy efficient curve[6] which shows the optimal implementations in
the energy-delay plane is shown in fig.1. By sizing the gates using logical effort we
minimized delay to reach point 0. Although we get delay reduced but energy is
increased, in order to reach the optimized point 1 we have to use certain optimization
technique which will complete our goal.
In this paper, we proposed a model based on logical effort and optimization tech-
nique to get proper trade-off between energy and delay in digital CMOS circuits.
Energy-Delay-Gain (EDG) is used to get the optimized value of energy and delay as
in [6]. But in this paper, we developed a relationship between energy and logical ef-
fort model which is used for optimization. We used logical effort method to reduce
the delay to minimum value but it will give larger power dissipation. To achieve
proper trade-off between energy and delay we formulated a problem which can be
solved using geometric programming.
The paper is organized as follows: Section 2, describes the method to obtain delay
efficient design. Section 3, illustrates the dependence of power on logical effort (g)
and electrical effort (h). In section 4, energy equation has been derived and the energy
delay (EDG) model is introduced. Section 5, discusses the optimization technique.
Finally, a conclusion is presented in the last section.
2
Delay Efficient Design
In order to get delay efficient circuit we sized the gates using logical effort technique.
Logical effort is a design methodology for estimating the delay of CMOS logic cir-
cuits. The method also specifies the proper number of logic stages on a path and the
best transistor sizes for the logic gates.
Using logical effort delay can be expressed as in [3] given by:
d = (gh + p)
˄
(1)
Where,
g = logical effort, h = electrical effort, p = parasitic delay, ˄ = basic delay unit
2.1
Calculation of Delay for Single Inverter
In the delay expression, to get the value of the electrical effort we require to find the
input capacitance of an inverter
