Information Technology Reference
In-Depth Information
Convex Optimization of Energy and Delay Using Logical
Effort Method in Deep Sub-micron Technology
Sachin Maheshwari, Rameez Raza, Pramod Kumar, and Anu Gupta
Department of Electrical and Electronics Engineering, BITS, Pilani, India
{sachin.mahe,rameez.alig,pramodkumarchennoju}@gmail.com,
anug@pilani.bits-pilani.ac.in
Abstract.
Tradeoff between the power dissipation and speed is one of the major
issues in modern VLSI circuit design. Improving the circuit speed methods typ-
ically lead to excessive power consumption. In this work, we explore the ener-
gy-delay design in CMOS circuits, to find gate sizes which produce the lowest
possible energy and delay. Our analysis methods include delay minimization
using logical effort, formulating energy relationship with logical effort model
and then optimizing the energy-delay using optimization technique. Thus, we
introduce the Energy-Delay-Gain (EDG) to measure the energy reduction rate
for each delay increase that is acceptable by the designer. The simulation is
done using Spectre in cadence environment in UMC90nm CMOS technology.
Keywords:
convex optimization, delay, energy-delay-gain, logical effort,
deep-sub-micron technology.
1
Introduction
The logical effort model is used commonly to estimate the delay of logic gates [1],
[2],[3].But the model used will not provide proper energy performance of the digital
circuits. Energy optimization can be achieved with equalization of sensitivities to
sizing, supply and threshold voltage compared to the reference design sized for mini-
mum delay [4].
In [5] a simple and yet accurate closed-form expression for power estimation
has be developed for CMOS gates but the method does not incorporate the effect of
parameters like change in library, rise and fall time of input, etc.
Fig. 1.
Energy Efficient Curve
