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they are activated to 'active mode'. Thus goal of power gating is to minimize leakage
power by temporarily shutting down power supply to selective blocks that are not
required in that mode. To reduce leakage power in power gating technique, high_V
T
(high threshold voltage)
PMOS transistor (sleep transistor) is used as header switches
to shut off power supplies to parts of a design in standby or sleep mode. NMOS footer
switches can also be used as sleep transistors.
Power gating structure for reduction of peak current and voltage glitch in system-
on-chip environment is presented in [2]. The author of [3] presented multi way circuit
partitioning strategy using genetic algorithm. Synthesis of finite state machine for low
power dissipation including circuit partitioning and state encoding based on genetic
algorithm (GA) has been reported in [4]. The author of [5] presented the state parti-
tioning and state encoding strategy targeting low power Finite State Machine (FSM)
decomposition based on GA approach to reduce leakage power as well as average
power. In [6] authors have implemented new probabilistic power model of the power
gated design of FSM and also GA is used to solve the problem of bi-partitioning and
encoding of FSM. But in [6] authors did not implement circuit level architecture, they
only implemented hypothetical architecture of PG, modelled the power and parti-
tioned FSM to two sub-FSMs and encoded the states based on GA using power gating
technique to save power. Here, new generic architecture of FSM based power gating
technique has been proposed and multilevel realisation also have been done for saving
power. A FSM is partitioned into two sub-FSMs and states are encoded based on
genetic algorithm (GA) which is described in [6]. Proposed PG architecture is imple-
mented in CADENCE virtuoso spectre at 45 nm technology. In this technique at a
time only one sub-FSM is in power gated mode and other one is in active mode, so
total power dissipation is less than the no power gating technique.
1.2
Within_Clock_ Power_Gating (WCPG)
FSM based power gating technique is used to reduce standby leakage and dynamic
power by shutting down the power supply of the inactive block of the circuit but the
active blocks continues to dissipate power. Leakage power of this active block also
can be minimized by applying power gating within the clock cycle during the idle
period if the clock period is larger than the critical path delay of the combinational
part. Basic principle of this sub-clock power gating technique has been described in
[7]. Author of [7] presented the sub-clock power gating technique to minimizing leak-
age power during active mode of combinational logic by concurrently frequency scal-
ing and voltage scaling whereas traditional power gating technique applied in idle
period. By frequency scaling leakage power reduces because if circuit operates at
maximum operating frequency then there is no idle time within the clock period but if
circuit operates at less than the maximum frequency then there is idle time present. As
there is no switching in this idle period, leakage power reduces. In [7], actual imple-
mentation of PG architecture in circuit level is not done properly. In [8], the proposed
technique, termed as within clock power gating (WCPG) technique has been imple-
mented for minimizing leakage and total power of the sequential circuits during active
mode of operation.
