Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG) - VLSI Design and Test - page 160

Power Reduction by Integrated Within_Clock_Power
Gating and Power Gating (WCPG_in_PG)
Debanjali Nath * , Priyanka Choudhury, and Sambhu Nath Pradhan
Department of ECE, NIT Agartala, Agartala, Tripura-799055, India
{nath.debanjali,priyanka.choudhury22,sambhu.pradhan}@gmail.com
Abstract. Leakage and switching power of circuit can be minimised in FSM
based power gating technique by partitioning and encoding of FSM. Depending
on the state of machine, at a time one sub-FSM is in power gated mode, but
other one is in active mode which continues to dissipate power. In active
sub-FSM, it is possible to reduce leakage, if the clock period is larger than the
critical path delay of the sub-FSM, then there is a certain portion within the
clock period which is idle and in this period power gating may be used. The ob-
jective of the paper is to reduce leakage power of active sub-FSM and to
reduce leakage and switching power of inactive sub-FSM. So, this paper
presents a new architectural technique, called WCPG_in_PG to minimize the
overall power. WCPG_in_PG architecture of ISCAS89 benchmark circuit has
been implemented and simulated in CADENCE VLSI tool at 45nm technology.
Keywords: Architecture, finite state machine (FSM), partitioning, encoding,
power gating, within-clock, custom implementation, low power.
1 Introduction
Power dissipation has become an important consideration as performance and area for
VLSI Chip design. Many techniques have been developed over the past decade to
address the continuously aggressive power reduction requirements of most of the high
performance VLSI systems. To reduce power, clock gating is one of the low power tech-
niques which disables some portions of the circuitry so that its flip-flops do not change
state; their switching power consumption goes to zero. The clock gating technique based
on finite state machine decomposition for low power has been reported in [1]. In this
clock gating technique leakage power is quite insignificant as compared to the dynamic
power. But in today's technology leakage power consumption is becoming high with
respect to the total power consumption of the circuit. To reduce leakage power, power
gating is one of the effective low power technique by shutting down the power supply
of inactive block.
1.1 Power Gating (PG)
This section briefly describes the power gating technique. Power gating is used to
reduce the overall leakage power of the chip by temporarily turning off the circuit
blocks that are not in use. When circuit blocks are required for operation, once again
* Corresponding author.