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As shown in Fig. 5, Subthreshold slope increases linearly whereas DIBL was found
increasing in discontinuous steps. Both these trends testify that for better perfor-
mance, one should keep the fin width as low as possible. AC small signal simulation
at 50GHz reveals that gate capacitance
C
gg
increases linearly as we augment the fin
width. Transconductance will also build up with the fin width as shown in Fig. 6.
Fig. 6.
Effect of fin width on transconductance and gate capacitance
All the parameter variations observed here are in closer agreement with those
proposed in [11] for long channel devices devices.
3.2
Impact of Graded Channel Doping
Asymmetric channel devices have been studied thoroughly by many authors [12]
[13]. In all those works, the channel is divided into two regions and heavy doping is
assigned near to Source allowing the channel region near Drain to act as a Lightly
Doped Drain (LDD). In this work, we, for the first time, investigated the performance
variation of 22nm FinFET under two different graded channel conditions. Table 2
shows the doping profiles selected for these simulations.
Comparison of
I
d
-V
g
characteristics for constant doping with GC1 and GC2 is
elucidated in Fig. 7. It is to be noted that in this section, constant doping refers to a
Boron channel doping of value 1E16 cm-3, unless otherwise specified.
Table 2.
Graded channel profiles selected for simulations
Nomenclature
Region 1
Region 2
Region 3
1E18 cm
-3
1E16 cm
-3
1E14cm
-3
GC1
1E14 cm
-3
1E16cm
-3
1E18cm
-3
GC2
