A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-Tox in CMOS VLSI Circuits - VLSI Design and Test - page 149

3-input NAND gate that substantially reduces the subthreshold leakage without
considerable reduction in gate leakage. Therefore, it can be preferred to replace the
PMOS transistors having lower T ox by using the PMOS transistors having higher T ox .
It reduces the gate leakage as well as the subthreshold leakage of a two-input NAND
gate. Apart from this, pin reordering is also referred as an effective technique for
leakage reduction that can be applied after each replacement of gate.
The conventional mechanism [5] has used the technique to replace a gate at WLS
in topological order. Using this approach, the outputs of the replaced gates have been
changed that affects the leakages of fan out gates which are again considered for
replacement. While moving towards the lower technology nodes, the gate leakage
substantially dominates the subthreshold leakage that affects the fan in gates.
Therefore, it is required to consider the leakage of fan out as well as fan in gates for
replacement. Thus, using the modified algorithm as depicted in Fig. 1, the
replacement has to be done for the gates from output towards the input by considering
the effect of leakage on fan in gates.

3 Analysis of Leakage Currents

Using the above mentioned gate replacement algorithm, this section analyzes the
reduction in leakage currents for different oxide thickness ( T ox ), transistor widths ( w )
and benchmark circuits.

3.1 Analysis of Leakage Current for Different Oxide Thickness

The gate oxide leakage is primarily referred as a strong function of gate oxide
thickness. Therefore, the variation of oxide thickness results in tremendous impact on
the gate leakage current. The higher oxide thickness in noncritical paths reduces the
gate leakage along with the subthreshold leakage while the lower oxide thickness in
critical paths maintains the performance of the circuit. The variation of normalized
leakage and delay for different oxide thickness is shown in Fig. 2(a). To reduce the
complexity of the approach, an appropriate value of T ox is selected among the set of
values presented in Table 1 . From these values, it is observed that the leakage current
reduces with a slight delay penalty. For analysis, the value of T ox for a PMOS
transistor is selected as 2nm. To overcome delay penalty, width of the PMOS
transistor is varied in the range of 135nm to 140nm for a fixed value of T ox = 2nm.
Figure 2(b) exhibits the normalized leakage and delay for different widths of PMOS
transistors. Using the data presented in Table 2, the suitable value of the width for a
PMOS transistor can be selected as 137nm. This quantitative value significantly
reduces the delay with a negligible effect on the leakage of the circuit as presented in
Fig. 2(b).