Information Technology Reference
In-Depth Information
2.2
Modified Gate Replacement Technique for Dual-
T
ox
Circuits
The conventional gate replacement technique [5] efficiently reduces the subthreshold
leakage without considerable reduction in gate leakage. Theoretically, the probability
of electron tunneling can be referred as a strong function of the oxide thickness
(
T
ox
).
Therefore, a small change in
T
ox
can have a tremendous impact on gate leakage. Using
this concept, the transistors with higher gate leakage can be replaced by the transistors
with higher
T
ox
values [7]. The different quantitative values of
T
ox
limits the
application of this approach, thus, it is required to find a most appropriate value of
T
ox
that will effectively reduce the gate leakage with lesser delay penalty.
Input:
{
G
1
, G
2
, ….
G
n-1,
G
n
}: gates in a circuit arranged in topological order
Output:
a circuit of the same functionality in active mode along with lower leakage in standby
Modified gate replacement algorithm
∈
1.
for
each gate
G
i
{
G
n
, G
n-1
, G
n-2
,………G
2,
G
1
}
2.
if
(
G
i
is at WLS and not marked )
3.
replace
G
i
temporarily
4.
if
(Total leakage reduces)
5.
Apply pin reordering
6.
if
(Total leakage reduces)
7.
Make the changes permanent and move to next gate
G
i+1
at WLS
8.
else
go to next step
∈
9.
{
G
i-1
, G
i-2
, G
i-3
,………G
n-1,
G
n
}
10.
if
(
G
j
is at WLS and not marked yet )
11.
replace
G
j
temporarily
12.
if
(Total leakage reduces)
13.
Apply pin reordering
14.
if
(Total leakage reduces)
15.
Make the changes permanent and move to next gate
G
j+1
at WLS
16.
else
go to next step
17.
else
mark and move to next gate in
G
m
till all gates in
G
m
are marked
18.
else
move to next gate in
G
m
until all gates in
G
m
are marked
19.
else
move to next gate in
G
i
until all gates in
G
i
are marked
e
lse
for each gate
G
j
Fig. 1.
Pseudo code of the modified gate replacement algorithm
The increasing
T
ox
reduces the gate leakage while the overall propagation delay of
the CMOS circuitry increases. One of the exciting solution to reduce the delay penalty
is to increase the width of the transistor. Using this approach, a modified gate
replacement technique can be applied after choosing some optimum value of
T
ox
on
basis of the leakage and delay trade off. For an instance, the stacking effect of NMOS
transistor in off state produces lower subthreshold leakage for a two-input NAND
gate, whereas the PMOS transistors produces higher gate leakage if all the inputs are
at higher potential. For this purpose, a 2-input NAND gate can be replaced using a
