A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-Tox in CMOS VLSI Circuits - VLSI Design and Test - page 147

Subthreshold leakage occurs due to the weak inversion region created between the
drain and source terminals when the gate voltage is lower in comparison to the V th .
Gate leakage is the adverse effect of aggressive scaling of the oxide thickness that
gives rise to higher electric fields. The high electric fields results in tunneling of
electrons (or holes) from the substrate to gate through the gate oxide potential barrier.
On the other hand, the reverse biased pn junction leakage can be referred as a
continuum effect of higher electric fields across reverse-biased pn junction. It causes
the tunneling of electrons from valence band of p region to the conduction band of n
region. This leakage is negligible compared to the subthreshold and gate oxide
leakages [2-6] for the technology nodes considered throughout the research paper.
This research paper primarily focuses on the reduction of leakage current by
applying the gate replacement technique that uses dual- T ox transistors. A novel
algorithm is proposed using the modified technique that replaces the gates having
higher leakage currents with the gates incorporating an extra sleep signal along with
the dual- T ox transistors [7]. Using this extra signal, it is observed that the functionality
of the VLSI circuit is maintained in the active mode while the leakage is reduced both
in the standby and active mode. Furthermore, pin reordering is applied that exhibits an
inexpensive approach for leakage reduction [8, 9]. The organization of this paper is as
follows: Section 1 introduces the briefs about the novel approach of leakage reduction
mechanisms. The mechanisms of leakage reduction using conventional [5] and
modified gate replacement techniques along with the dual- T ox transistors are presented
in section 2. Section 3 analyzes the HSPICE simulated results for different benchmark
circuits at 45nm technology node. Finally, section 4 draws a brief summary of this
paper.

2 Leakage Reduction Techniques

This section provides a detailed description of leakage reduction by using the gate
replacement method. A logic gate can be considered at its worst leakage state (WLS)
when its input state yields highest leakage current [5, 10, 11]. Using the gate
replacement, a modified gate replacement technique is presented to reduce the
leakages. This modified technique follows the conventional gate replacement
mechanism using the stacking effect along with dual- T ox transistors.

2.1 Basic Gate Replacement Technique

Using basic gate replacement technique, the logic gate at WLS is replaced by
another gate containing an extra sleep signal. When the circuit is in active mode i.e.
SLEEP = 1, this condition exhibits the correct functionality of the circuit. On the other
hand, when the circuit is in standby mode, i.e., SLEEP = 0, this condition reduces the
leakage current of the replaced gate. This process may change the output of the
replaced gate. This replacement technique may affect the leakage of other gates too,
which are again considered for replacement [5].