A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-Tox in CMOS VLSI Circuits - VLSI Design and Test - page 146

A Modified Gate Replacement Algorithm for Leakage
Reduction Using Dual- T ox in CMOS VLSI Circuits
Surabhi Singh, Brajesh Kumar Kaushik, and Sudeb Dasgupta
Microelectronics and VLSI Group, Department of Electronics and Communication Engg.
Indian Institute of Technology Roorkee, Roorkee - 247667, India
[e-mail], {bkk23fec,sudebfec}@iitr.ernet.in
Abstract. This research paper presents different leakage mechanisms including
the subthreshold and gate leakage current that occurs due to the aggressive
scaling in nanoscale CMOS VLSI circuits. A novel algorithm is proposed based
on the conventional gate replacement technique that is used to reduce the
leakage current in CMOS VLSI circuits. This technique employs the stacking
effect using dual- T ox transistors. This approach is more effective for lower
technology nodes wherein the gate leakage dominates the subthreshold leakage.
The stacking effect, used with dual- T ox transistors, efficiently reduces the gate
and subthreshold leakage in both the standby and active mode. Apart from this,
leakage current can be further reduced using the pin reordering technique.
Using these techniques, the modified gate replacement algorithm is applied for
technology nodes below 65nm that reduces the overall leakage current by
39.9% in standby mode.
Keywords: Leakage current, benchmark circuits, gate replacement, subthreshold
leakage, gate leakage, dual- T ox , VLSI.
1 Introduction
For the last few decades, CMOS devices have been scaled down to achieve higher
packing density and improved performance. In order to maintain the power
consumption under control, supply voltage ( V dd ) of CMOS devices is scaled down.
However, threshold voltage ( V th ) has to be commensurately scaled to maintain a high
drive current and to achieve an improved performance [1]. The reduced V th results in
substantial increment of leakage current of a CMOS VLSI circuit. Consequently, in
order to keep the driving capability of gate at considerable level, it is desirable to
reduce the gate oxide thickness ( T ox ) that results in gate tunneling leakage. Therefore,
gate and subthreshold leakage currents have significant contributions in power
dissipation at nanoscale VLSI circuits [1, 2].
In nanometer regime, the leakage current is primarily dominated by the
subthreshold, gate and reverse-biased pn junction leakage current [2]. In addition to
these three major leakage components, gate-induced drain leakage, punch-
through current and gate leakage due to hot-carrier injection also degrades the
device performance with a negligible effect in current technology nodes [3].