An Improved gm/ID Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design - VLSI Design and Test - page 134

Improved g m /I D Methodology 3.2

The chosen two stage Miller OTA circuit is shown in Fig.5. Considering the
dependence of the Early voltage parameter V A on the operating bias conditions
of the MOS transistor, the improved g m /I D methodology for the design of a
nano-scale CMOS OTA circuit is shown in Fig. 6. The input specifications are
the desired gain, bandwidth, phase margin and power consumption of the circuit.
Depending upon the magnitude of the desired gain, the channel length of the
MOS transistors are to be fixed. For moderate gain 60 dB , the channel length

may be considered to be 100nm. However, if larger gain is required, the channel
length needs to be increased. The bias current is fixed depending upon the
power consumption requirement of the circuit. The design process starts with
initialization of bias points for all the transistors such that these operate in
the weak inversion region and the total potential drop across any branch of
the circuit, starting from the supply to the ground does not exceed the supply
voltage. The g m /I D and the Early voltage parameter V A of each transistor are
computed from the corresponding look up tables. Since the g m /I D and the drain
current I D of each transistor are known, the corresponding g m s are computed.In
order to satisfy the desired gain, the bias voltages are adjusted and the procedure
is iterated until the desired gain is achieved. Next the compensation capacitor
C c and the nulling resistor R c are determined as follows [7]

g m 1
2 ˀUGB

C c = (4)

C c + C L
C c

1
g m 7

R c = (5)

In order to achieve the desired gain bandwidth and the phase margin, the values
of the compensation capacitor and the nulling resistor are adjusted. Once all the
desired specification are met and the g m /I D and I D of all transistors are known,
the corresponding aspect ratios are determined.
The major advantages of the present g m /I D methodology over the traditional
methodology are as follows

1. The dependence of the Early voltage parameter on the operating bias points
of the transistor are considered in the design process. This is utilized to
obtain the desired gain, keeping the channel length constant. Thus the total
area of the circuit is not unnecessarily increased.
2. The bias voltages of the input transistors are determined automatically
rather than to find out through trial and error method as done for the
traditional methodology.

4 Results and Discussion

The desired specifications are (1) gain A v > 60 dB ,(2) UGB > 45 KHz ,(3)
PM > 55 0 and (4) power dissipation P< 350 nW . The chosen CMOS technology
is 45-nm with supply voltage of 1V. The circuits are simulated with BSIM4