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to be satisfied by biasing the transistors in the weak inversion region and varying
the channel length. But this in many cases, increase the area of the circuit.
This paper presents an improved
g
m
/I
D
methodology where the explicit de-
pendence of the Early voltage parameter on the operating bias points is taken
into considerations. It has been shown through simulation results that this pa-
rameter significantly depends upon the drain bias for nano-scale MOS transis-
tors. This is because of the combined effects of the channel length modulation
and drain induced barrier lowering phenomenon. This dependence is utilized to
obtain the desired gain, keeping the channel length constant. Thus the total
area of the circuit is not unnecessarily increased. The bias voltages of the input
transistors are determined automatically rather than to find out through trial
and error method as done for the traditional methodology.
2 The Traditional
g
m
/I
D
Methodology
The
g
m
/I
D
based circuit sizing procedure is based on the relation between the
ratio of the transconductance over dc current
g
m
/I
D
and the normalized current
I
N
=
I
D
/
(
W/L
). The relation between the
g
m
/I
D
parameter with the operating
region of the transistor may be written as follows
∂
ln
I
DS
(
L
)
g
m
I
D
=
1
I
D
∂V
GS
=
∂
(ln
I
D
)
∂I
D
=
(1)
∂V
GS
∂V
GS
The maximum value of the
g
m
/I
D
ratio is observed to be in the weak inversion
region and the value decreases as the operating point moves toward strong in-
version when
V
GS
is increased as shown in Fig. 1(a) It may be noted that the
relationship between the
g
m
/I
D
ratio and
V
GS
is independent of the transistor
sizes. Therefore, this relationship is a unique characteristic for all transistors of
the same type (n-channel MOS or p-channel MOS) in a given batch. This is
shown in Fig. 1(b). The universal characteristic of the
g
m
/I
D
versus
I
N
curve
(shown in Fig. 2 ) is used to determine the aspect ratio of a transistor, which is
then subsequently used to determine the channel width, assuming a fixed value
of the channel length.
For a MOS transistor, the magnitude of the intrinsic voltage gain is given by
A
v
=
g
m
r
0
=
g
m
I
D
(
I
D
r
0
)=
g
m
I
D
V
A
(2)
where
V
A
is referred to as the Early voltage of the transistor. Assuming
V
A
to
be constant for a particular channel length of a transistor, the intrinsic gain is
determined by the
g
m
/I
D
ratio. Therefore, the intrinsic gain of a MOS transistor
is maximum in the weak inversion region and reduces as the operating point
moves towards the strong inversion region. Therefore, an important guideline to
get high gain for a MOS transistor, is to bias the transistor in the weak inversion
region with as low
V
GS
as possible. Under weak inversion region very small
