An Improved gm/ID Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design - VLSI Design and Test - page 128

An Improved g m /I D Methodology
for Ultra-Low-Power Nano-Scale CMOS
OTA Design
Somnath Paul, Abhijit Dana, and Soumya Pandit
Institute of Radio Physics and Electronics, University of Calcutta, Kolkata India
[e-mail]
Abstract. This paper presents an improved g m /I D methodology for
the design of low-power CMOS operational transconductance amplifier
(OTA) circuit using nano-scale CMOS technology. This methodology
takes into considerations the dependence of the Early voltage parameter
with the bias points of a nano-scale MOS transistor. With such consider-
ations, the DC voltage gain of the circuit can be controlled by adjusting
the bias points of the transistors and keeping the channel length con-
stant. The advantage of the improved methodology over the traditional
methodology has been discussed and illustrated with simulation results.
Keywords: Nano-scale, g m /I D , Early Voltage, DIBL, OTA.
1 Introduction
The design of integrated circuits with ultra-low power dissipation is becoming
an essential requirement considering the fact that most of the present day ap-
plications are battery operated [1]. In addition, with the scaling of transistor
dimensions in nano-scale CMOS technology, it is becoming important to design
with low supply voltage for better reliability of the integrated circuits. The main
drawback associated with the scaling of supply voltage with technology genera-
tion is that the threshold voltage of MOS transistors do not scale as such with
technology generation. Therefore, the design of nano-scale analog circuits with
scaled supply voltage, is although an essential requirement, is extremely chal-
lenging. In the design of analog integrated circuits, the step of selecting device
sizes and biases is crucial to enhance the final performance, power, and yield of
the circuits. The g m /I D methodology [2,3] enables the designers to fix currents
and transistors widths of CMOS analog circuits so as to meet specifications such
as gain-bandwidth while optimizing attributes like low power and small area.
The sizing method takes advantage of the transconductance g m to drain current
I D ratio and makes use of either 'semi-empirical' data or compact models. The
traditional g m /I D methodology does not explicitly consider the dependence of
the Early voltage parameter upon the operating bias points of the transistor [4].
The Early voltage parameter is considered to be constant depending upon the
chosen channel length of the transistor. Therefore, the gain specification is tried