Information Technology Reference
In-Depth Information
References
1. Colinge, J.P., Lee, C.W., Afzalian, A., Akhavan, N.D., Yan, R., Ferain, I., Razavi, P.,
O'Neill, B., Blake, A., White, M., Kelleher, A.M., McCarthy, B., Murphy, R.: Nanowire
Transistors Without Junctions. Nature Nanotechnology 5, 225-229 (2010)
2. Lee, C.W., Afzalian, A., Akhavan, N.D., Yan, R., Ferain, I., Colinge, J.P.: Junctionless
Multigate Field - Effect Transistor. Applied Physics Letters 94, 053 511-1-053 511-2
(2009)
3. Lee, C.W., Afzalian, A., Akhavan, R., Ferain, N.D., Yan, I., Razavi, P.R., Doria, R.T.,
Colinge, J.P.: Low Subthreshold Slope in Junctionless Multigate Transistor. Applied
Physics Letters 96, 102106 (2010)
4. Lee, C.W., Ferain, I., Afzalian, A., Yan, R., Akhavan, N.D., Razavi, P., Colinge, J.P.:
Performance estimation of junctionless multigate transistors. Solid-State Electronics 54,
97-103 (2010)
5. Doria, R.T., Pavanello, M.A., Trevisoli, R.D., de Souza, M., Lee, C.W., Ferain, I.,
Akhavan, N.D., Yan, R., Razavi, P., Yu, R., Kranti, A., Colinge, J.P.: Junctionless
Multiple - Gate Transistors for Analog Applications. IEEE Trans. Electron Devices 58,
2511-2519 (2011)
6. Cho, S., Kim, K.R., Park, B.G., Kang, I.M.: RF performance and small signal parameter
extraction of junctionless silicon nanowire MOSFET. IEEE Trans. Electron Devices 58(5)
(2011)
7. Lou, H., Zhang, L., Zhu, Y., Lin, X., Yang, S., He, J., Chan, M.: A Junctionless Nanowire
Transistor with a Dual-Material Gate. IEEE Trans. Electron Devices 59(7), 1829 (2012)
8. Razavi, P., Orouji, A.A.: Dual Material Gate Oxide Stack Symmetric Double Gate
MOSFET: Improving Short Channel Effects of Nanoscale Double Gate MOSFET. In: Int.
Biennial Baltic Electronics Conference (2008)
9. Long, W., Ou, H., Kuo, J.-M., Chin, K.K.: Dual - Material Gate (DMG) Field Effect
Transistor. IEEE Trans. Electron Devices 46(5), 1829 (1999)
10. Ghosh, P., Haldar, S.R., Gupta, S., Gupta, M.: Analytical Modeling and Simulation for
Dual Metal Gate Stack Architecture (DMGSA) Cylindrical/Surrounded Gate MOSFET. J.
of Semiconductor Technology and Science 12(4) (2012)
11. Kasturi, P., Saxena, M., Gupta, M., Gupta, R.S.: Dual Material Double - Layer Gate Stack
SON MOSFET: A Novel Architecture for Enhanced Analog Performance—Part I: Impact
of Gate Metal Workfunction Engineering. IEEE Trans. Electron Devices 55(1), 372-381
(2008)
12. Kasturi, P., Saxena, M., Gupta, M., Gupta, R.S.: Dual Material Double-Layer Gate Stack
SON MOSFET: A Novel Architecture for Enhanced Analog Performance—Part II: Impact
of Gate - Dielectric Material Engineering. IEEE Trans. Electron Devices 55(1), 382-387
(2008)
13. Park, J.C., Lee, H.N.: Improvement of the Performance and Stability of Oxide
Semiconductor Thin - Film Transistors Using Double-Stacked Active Layers. IEEE Trans.
Electron Devices 33(6), 818-820 (2012)
14. Kumar, M., Chaudhry, A.: Two - dimensional analytical modelling of fully depleted DMG
SOI MOSFET and evidence for diminished SCEs. IEEE Trans. Electron Devices 51(4),
569-574 (2004)
15. Chakraborty, S., Mallik, A., Sarkar, C.: Subthreshold performance of dual-material gate
CMOS devices and circuits for ultralow power analog/mixed-signal applications. IEEE
Trans. Electron Devices 55(3), 827-832 (2008)
Search WWH ::




Custom Search