Information Technology Reference
In-Depth Information
3.0
100
DM-DGS
DMG
SMG
2.5
80
2.0
60
1.5
40
1.0
20
0.5
0
0.0
0.0
0.2
0.4
0.6
0.8
1.0
Drain Voltage, V
DS
(V)
Fig. 5.
Output conductance (G
D
) and early voltage (V
EA
) with respect to gate voltage for the
devices at V
DS
= 1 V for L =40 nm, T
si
=8 nm and T
ox
=2 nm
60
DM-DGS
DMG
SMG
56
52
48
44
40
36
32
28
0.0
0.2
0.4
0.6
0.8
1.0
Gate Voltage, V
GS
(V)
Fig. 6.
Intrinsic gain (G
m
R
O
) with respect to gate voltage for the devices at V
DS
= 1 V for L =40
nm, T
si
=8 nm and T
ox
=2 nm
Fig. 5 presents the output conductance G
D
(=∂I
D
/∂V
DS
) variation of the devices
with drain voltage, V
DS
for a fixed value of V
GS
=1 V. The DM-DGS DGJLT carries
higher output current and hence output conductance compared to other two devices.
At low V
DS
(till ~ 0.55 V), output conductance is governed by channel length
modulation (CLM) and at higher V
DS
, it is governed by drain induced barrier lowering
(DIBL), if impact ionization is not taken into account [11]. Thus, the curve brings out
that DM-DGS architecture has lower values of CLM and DIBL compared to DMG
