Characterization of Logical Effort for Improved Delay - VLSI Design and Test - page 117

4 Conclusion

In this report a simple delay characterization using logical effort for inverter have
been done using UMC90nm technology. The new logical effort values obtained for
basic universal gates gives minimum delay when validated on a chain of inverters
compared with the existing logical effort. From table 5, it is quite evident that the
proposed skewed gate shows much improvement when compared with existing
skewed logic and from table 6, the proposed skewed logic favoring a particular transi-
tion shows much improvement over existing skewed logic. Thus, we can conclude
that to get minimum delay and reduced area one can use the proposed low skewed
gate in designing a logic for minimum delay.

Acknowledgement. The authors are grateful to the lab facilities (Oysters Lab) of
Department of Electrical & Electronics Engineering at Birla Institute of Technology
& Science (BITS), Pilani where the work has been carried out.

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