Information Technology Reference
In-Depth Information
Fig. 9.
Chain of inverters favoring high transition
Table 5.
Delay Comparison
Rising
Delay (ps)
Falling
Delay (ps)
Average
Delay (ps)
Percentage
Improvement (%)
Normal Skewed
65.90
72.60
69.25
---
High Skewed
86.20
102.80
94.50
-36.46
Low Skewed
61.80
54.90
58.35
15.74
Proposed High Skewed
60.00
63.40
61.70
10.90
Proposed Low Skewed
57.80
53.60
55.70
19.57
To get the better result various simulation were conducted and the results are tabu-
lated in table 5 and table 6. First set consist of normal skewed chain-of-inverter with
each inverter having 2:1 PMOS to NMOS width ratio, high skewed and low skewed
chain of inverters and proposed high skewed and low skewed chain of inverters.
Every path through a network of logic gate will experience alternating rising and fall-
ing transition and the results are tabulated in table 5, whereas, second set consist of
alternate high and low skewed gates favoring a particular transition and the results are
tabulated in table 6. The final output decides whether the transition is falling or rising.
Table 6.
Delay Comparison of Favoring Transition
Favoring
Transition
Rising Delay
(ps)
Falling
Delay (ps)
Average
Delay (ps)
Percentage
Improvement (%)
High
41.30
144.30
92.80
----
Low
135.50
40.70
88.10
----
Proposed High
49.50
89.90
69.70
24.89
Proposed Low
90.40
48.70
69.55
21.06
