Characterization of Logical Effort for Improved Delay - VLSI Design and Test - page 115

Fig. 8. NOR gate for rising delay

For UMC 90nm, the values used are ʼ =2, The values for K P are empirical, and
come from an analysis of the logical effort of NOR gates from various standard cell
libraries. The fastest NOR gate occurs when;

dg

(14)

=− K μγ

2

= 0

P

d γ

(15) γ = μ K

P

From simulations a similar result for K P can be deduced, taking the ʳ = 1.4 (as of
inverter). The delay values are shown in the table 4.

Table 4. Average Delay for various values of K P

K P Falling delay (ps) Rising delay (ps) Average delay (ps)

1.000 12.16 25.96 19.06

1.125 13.09 24.56 18.83

1.250 14.00 23.35 18.68

1.375 14.81 22.27 18.54

1.500 15.55 21.34 18.45

1.625 16.28 20.60 18.44

1.750 16.97 19.89 18.43

1.875 17.65 19.14 18.39

2.000 18.30 18.62 18.46

The value of K P comes out to be 1.875 (15/8). For this value the logical effort of a
2-input NOR gate is 1.2946.

3 Validation

For validating the above sizing, 5-stage chain of inverters was design at 500MHz
using BSIM3 models of UMC90nm CMOS process in Cadence design environment at
1V power supply. Fig. 3 shows a chain of inverters favoring high transition.