Information Technology Reference
In-Depth Information
(
)
μ
+
K
μ γ
μ
(7)
N
g
=
(
)
u
1
+
The logical effort g is then:
(
γ
+++
K
μ
(
μ γ
)
K
)
1
2
(8)
g
=
N
N
(1
+
μ
)
The fastest NAND gate is when
dg
(9)
2
=−
1
K
μγ
=
0
N
d
γ
(10)
The way of checking the result is consider the value of
ʳ
= 1.4 (as obtained for the
inverter) and then verifying the results for a K
N
from the delay obtained. The model
verified using simulation is shown in the table 3.
γ
=
K
μ
N
Table 3.
Average Delay for various values of K
N
K
N
Falling delay (ps)
Rising delay (ps)
Average delay (ps)
1.00
14.27
18.22
16.25
1.17
12.62
19.34
15.98
1.33
11.35
20.33
15.84
1.40
11.01
20.66
15.83
1.50
10.28
21.32
15.80
1.67
9.35
22.24
15.79
1.83
8.56
23.08
15.82
2.00
7.89
23.89
15.89
It is quite evident from table 3 that at K
N
= 1.67 = 5/3 the average delay is least.
This value of K
N
when applied to the formula of logical effort gives us the logical-
effort of NAND gate which is 1.242.
2.3
NOR Gate
The calculation of the logical effort for NOR gates follows a parallel path to the one
used for NAND gates. We size the series PMOS transistors so that their conductance is
the same as the single transistors in a reference inverter. We define the amount by which
the transistor must be increased as K
P
, the PMOS transistor conductivity coefficient.
In Logical Effort, Ohm's law is used so that K
P
is 2 for a 2-NOR gate, 3 for a 3-
NOR gate and 4 for a 4-NOR gate. It recognizes that this is a simplification, because
velocity saturation of the carriers means that series combinations of PMOS transistors
are more conductive than a single one. However, the lower speed of holes compared
to electrons means that the speed of the holes in a single PMOS transistor is not so
subject to velocity saturation effects, so that K
P
following Ohm's law is a more accu-
rate approximation than it was for NAND gates.
