Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology - VLSI Design and Test - page 105

The analysis of the KS adder is done at different process corners in UMC 90nm and
UMC180nm CMOS technology at particular temperature.

4 Simulation Results

The KS adder design was simulated using spectre in UMC 180nm and UMC90nm
technology with minimum sized two input gates that are carefully laid out to function
below the threshold voltage. The simulation was done for the worst case delay condi-
tion for all five corners are tabulated in table 1. The supply voltage used are 0.35V for
180nm and 0.2V for 90nm. Monte-Carlo simulations was also done for 100 points in
UMC180nm Technology. The transistor sizes taken are L=180nm and W=240nm.

Fig. 5. KS adder output bits v/s time using Monte Carlo Simulation for 100 points in
UMC180nm

Table 1. The worst case delay and power dissipation of kogge-stone adder at different process
corners in UMC 180nm

Power
Dissipation
(*10 -6 W)

Process
corners

Temperature
( 0 C)

Worst-case
delay(us)

Power-Delay-Product
(*10 -15 )

S.No.

1 TT 27 0.09 0.709 63.81

2 SS 100 0.14 0.505 70.70

3 FF 0 0.20 0.359 71.80

4 SNFP 27 0.26 0.513 133.38

5 FNSP 27 0.20 1.159 231.80