Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology - VLSI Design and Test - page 104

Fig. 4. Radix-2 32-bit Kogge-Stone adder with critical path

sum-generation gates. The schematic of radix-2 32-bit KS adder for with critical path
is shown in Fig. 4.
In KS adder generate and propagate signals are generated using AND logic and
XOR logic. Whereas, the new generate and propagate signal are generated as;

g new = g present + g previous * p present (1)

p new = p present * p previous (2)

Using this architecture, the carry bits can be generated in 5stages for 32-bit KS adder.

3.1 Worst Case Condition
Since, the carry is available for sum 16th to sum 31st at the same time, so the worst
case is when the carry delay is maximum for sum 16th bit.

out16 = g new16 + p new16 * C in

(3)

Since, g new and p new are available at the same instant of time hence the worst case is
dependent on the product term that is p new16 *C in . Also, C in is available with inputs, it is
totally dependent on p new16 .
Let us assume that initially, C in is logic 1, so as soon as the value of p new16 is logic
1 the C out16 is produced. p new16 depends on p0, p1, p2 upto p16. So, the inputs should
such that p new0 , p new1 , p new2 and so on upto p new15 should be logic 1. So the worst case
input combination is:

A = xxxxxxxxxxxxxxx11111111111111111

B = xxxxxxxxxxxxxxx11111111111111110

in =1