Digital Signal Processing Reference
In-Depth Information
For simple input signals, the error signal is well-correlated with the input signal, as can be seen in
Fig. 3.19, plots (c) and (d); when the input signal is complicated, the error signal will be less correlated
with the input, i.e., appear more random. Noise that correlates well with the input tends to be tonal
and more audible; there exist a number of methods to “whiten” the spectrum of the sampled signal by
decorrelating the sampling noise. One such method,
Dithering
, is to add a small amount of random
noise to the signal, which helps decorrelate sampling artifacts. Extensive discussions of dithering are
found in [1] and [2].
Quantization using 4 bits still results in objectionably large amounts of quantization noise, as
shown in Fig. 3.19, plots (c) and (d).
Note that no value of the signal to be quantized is ever further than one-half the LSB amount
from one of the possible quantized output levels. This can be seen clearly in Fig. 3.18, plots (c) and (d).
Recall that the LSB amount would be (170 volts/7 levels) = 24.2857 volts/level. Note that in Fig. 3.19,
plot (d), the maximum noise amplitude is about half that, or a little over 12 volts.
As a good approximation, it can be said that each time the number of quantizing bits goes up
by one, the maximum magnitude of quantization noise is halved, and the corresponding noise power is
quartered, since power is proportional to the square of voltage or amplitude.
References [1] and [2] give extensive and accessible discussions of quantization noise.
3.13
DAC WITH VARIABLE LSB
The eventual goal of much signal processing, such as that of audio or video signals, is to convert digital
samples back into an analog signal. This is the process of signal reconstruction, which is performed by
sending the digital samples (binary numbers) to a DAC.
In addition, as we have seen, the heart of a successive approximation converter is a digital-to-analog
converter.
Figure 3.20 depicts a typical arrangement for converting a sequence of digitized samples back into
an analog signal. The latch holds a digital word (typically 4-24 bits) on the input of the DAC until the
next digital word is issued from the digital sample source. Holding a value constant until the next one is
retrieved is referred to as a
Zero Order Hold
, which is discussed later in this chapter.
A simple DAC is shown Fig. 3.21. A reference voltage feeds binarily-weighted resistors that feed
the inverting input of an operational amplifier, which sums the currents and outputs a voltage proportional
to the current according to the formula
V
out
=
V
·
(Bit (
3
)(
−
R/R)
+
Bit(
2
)(
−
R/
2
R)
+
Bit(
1
)(
−
R/
4
R)
+
Bit(
0
)(
−
R/
8
R))
which reduces to
V
out
=−
·
+
+
+
V
(Bit (
3
)
0
.
5
Bit(
2
)
0
.
25
Bit(
1
)
0
.
125
Bit(
0
))
where
Bit(
0
)
means the value (1 or 0) of the 2
0
bit, and so forth. This scheme can be expanded to any
number of needed bits.
Here we see that for the type of DAC shown in Fig. 3.21,
V/(
2
N
−
1
)
LSB
volts
=−
(3.2)
