Digital Signal Processing Reference
In-Depth Information
Receiver 1
Receiver 2
1
11
D
1
24
D
cccc
,
,
,
s sss
,
,
,
11
12
13
14
21
22
23
24
D
1
12
1
23
D
Time slot 1
ssss
,
,
,
cccc
,
,
,
11
12
13
14
21
22
23
24
cccc
,
,
,
cccc
,
,
,
s sss
,
,
,
11
12
13
14
ssss
,
,
,
21
22
23
24
21
22
23
24
11
12
13
14
1
21
D
D
1
13
D
1
14
1
22
D
1
1
1
1
1
1
DDDDDD
,
,
DDDDDDDDDD
1
1
,
1
1
,
1
1
,
1
1
,
1
1
11
13
11
14
11
12
24
21
24
22
24
23
23
21
23
22
2
11
D
D
2
24
cccc
,
,
,
ssss
,
,
,
11
12
13
14
21
22
23
24
D
2
23
2
12
D
ssss
,
,
,
cccc
,
,
,
Time slot 2
11
12
13
14
21
22
23
24
ssss
,
,
,
s sss
,
,
,
cccc
,
,
,
cccc
,
,
,
21
22
23
24
11
12
13
14
11
12
13
14
21
22
23
24
2
14
2
22
D
D
D
2
21
2
13
D
2
2
2
2
2
2
DDDDDDDDDD
2
2
,
2
2
,
2
2
,
2
2
,
2
2
DDDDDD
,
,
24
21
24
22
23
24
11
13
11
14
11
12
12
13
12
14
3
23
D
3
12
ssss
,
,
,
D
cccc
,
,
,
11
12
13
14
21
22
23
24
D
3
11
D
3
24
cccc
,
,
,
ssss
,
,
,
Time slot 3
11
12
13
14
21
22
23
24
cccc
,
,
,
cccc
,
,
,
ssss
,
,
,
11
12
13
14
21
22
23
24
ssss
,
,
,
21
22
23
24
11
12
13
14
3
13
D
3
14
3
21
D
D
D
3
22
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
DDDDDD
,
,
DDDDDDDDDD
,
,
,
,
23
21
23
22
23
24
12
14
12
13
12
11
11
14
11
13
4
12
4
23
D
D
ssss
,
,
,
cccc
,
,
,
D
4
24
D
4
11
11
12
13
14
21
22
23
24
cccc
,
,
,
s sss
,
,
,
Time slot 4
11
12
13
14
21
22
23
24
ssss
,
,
,
ssss
,
,
,
cccc
,
,
,
11
12
13
14
21
22
23
24
cccc
,
,
,
21
22
23
24
11
12
13
14
D
4
14
D
4
22
4
13
4
21
D
D
DDDDDD
4
4
,
4
4
,
4
4
DDDDDDDDDD
4
4
,
4
4
,
4
4
,
4
4
,
4
4
12
13
12
14
11
12
23
21
23
22
23
24
24
21
24
22
Fig. 5.4
Illustration of our precoding scheme at 4 time slots
V
H
1
H
1
U
†
H
1
,
V
H
2
H
2
U
†
H
2
,
H
1
=
H
2
=
V
G
1
G
1
U
†
V
G
2
G
2
U
†
G
1
=
G
1
,
G
2
=
(5.49)
G
2
where
U
H
1
(
denote the eigenvectors corresponding to
the largest eigenvalues of
H
1
,
H
2
,
G
1
,
G
2
, respectively. Also we use
x
1
1
)
,
U
H
2
(
1
)
,
U
G
1
(
1
)
,
U
G
2
(
1
)
x
2
to denote
that vector
x
1
has the same direction as vector
x
2
. As shown in Fig.
5.4
, our precoder
design procedure can be summarized as follows:
1. At time slot 1, design precoder
A
1
. Design precoder
B
1
to make
D
11
U
H
1
(
1
)
D
11
. Design precoder
A
2
to make
D
13
⊥
to make
D
12
⊥
D
11
,
D
13
⊥
D
12
,
D
23
⊥
D
21
,
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