Digital Signal Processing Reference
In-Depth Information
sin
(
2
π
f
0
t
+
θ
)
sin
(
2
π
n
/
N
)
l
g
r
,
y
i
d
.
,
©
,
L
s
t
n
N
↓
Figure 12.25
A digital PLL with a sinusoidal input.
Normally, the sampling period is a constant and
T
[
n
]=
T
s
=
1
/
F
s
but here
we will assume that we have a special A
D converter for which the sampling
period can be dynamically changed at each sampling cycle. Assume the in-
put to the sampler is a zero-phase sinusoid of
known
frequency
f
0
=
/
F
s
/
N
for
N
∈
and
N
≥
2:
x
(
t
)=
sin
(
2
π
f
0
t
)
If the sampling period is constant and equal to
T
s
and if the A
/
Dissyn-
chronous to the sinusoid, the sampled signal are simply:
sin
2
N
n
x
[
n
]=
We can test such synchronicity by downsampling
x
[
n
]
by
N
and we should
have
x
ND
[
0forall
n
; this situation is shown at the top of Figure 12.26
and we can say that the A
n
]=
/
Dis
locked
to the reference signal
x
(
t
)
.
with respect to the reference time of
the incoming sinusoid (or, alternatively, if the incoming sinusoid is delayed
by
If the local clock has a time lag
τ
τ
), then the discrete-time, downsampled signal is the constant:
x
ND
[
n
]=
sin
(
2
π
f
0
τ
)
(12.33)
Note, the A
,butitexhibitsa
phase offset, as shown in Figure 12.26, middle panel. If this offset is suf-
ficiently small then the small angle approximation for the sine holds and
x
ND
/
D is still locked to the reference signal
x
(
t
)
provides a direct estimate of the corrective factor which needs to be
injected into the A
[
n
]
/
D block. If the offset is estimated at time
n
0
, it will suffice
to set
T
s
−
τ
=
for
n
n
0
T
[
n
]=
(12.34)
T
s
for
n
>
n
0
for the A
/
Dtobelockedtotheinputsinusoid.
