Baseband Hardware Designs in Modernised GNSS Receivers - Global Navigation Satellite Systems: Signal,Theory and Applications - page 33

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Baseband Hardware Designs in
Modernised GNSS Receivers
Nagaraj C. Shivaramaiah and Andrew G. Dempster
The University of New South Wales
Australia
1. Introduction
The Global Positioning System (GPS) receiver has come a long way from being a specialised
tool to a more general purpose everyday use mainstream gadget. This transformation is
not only due to the advancements in semiconductor technology and embedded systems but
also due to a highly concentrated research effort in the past decade that targeted a high
performance, low power and affordable GPS receiver design. Before the ideas for such an
efficient GPS receiver design could attain the saturation stage, the GPS modernisation and the
development of several satellite navigation systems under the broader “Global Navigation
Satellite Systems” (GNSS) umbrella, have brought a new dimension to the problem of efficient
GNSS receiver design. The baseband signal processing engine forms an integral part of any
GNSS receiver and is a key contributor to the overall cost and power consumption.
This chapter discusses the challenges involved in designing baseband signal processing
algorithms for a modernised GNSS receiver. The modernised GNSS receiver in this context
includes processing elements not only for the GPS civilian signals GPS L1C/A, GPS L2C, GPS
L5 and GPS L1C, but also for the Open Service (OS) signals from other satellite navigation
systems that share the same frequency band as that of GPS. The Galileo satellite navigation
system is one such example with its E1 and E5 OS signals sharing the GPS L1 and L5 (partial)
frequency bands respectively. Though the underlying concept used in all these signals is
“spread spectrum”, the structure of these signals differ due to different modulation techniques
and signal parameters such as chipping rate, spreading code length, signal bandwidth and
navigation data rate. These differences make the efficient baseband hardware design an
interesting and useful research topic.
The key objectives of this chapter are:
1. To revisit the existing efficient GPS L1 C/A baseband hardware methodologies and list
best practices / learnings,
2. To analyse the complexity of the modernised GNSS baseband hardware and to identify
key contributors to this complexity,
3. To explore design alternatives that deal with the key complexity contributors and to
analyse the implementation feasibility of these design alternatives,
4. To ascertain the practicality of incorporating the design alternatives by implementing them
on a FPGA based hardware platform, and