Reconfigurable Baseband Processing for Wireless Communications - Adaptive Signal Processing in Wireless Communications - page 470

15.5 Conclusion

Future wireless communication devices will contain integrated circuits where multiple
processing cores are implemented on one chip. These multiprocessor systems-on-chip
(MP-SoC) will be heterogeneous; they will consist of multiple types of processing cores.
Bit-level functions will be executed by FPGA-type processors, word-level functions by
coarse-grained reconfigurable processors, and control-oriented functions by GPPs. In
wireless communication systems, processing is dominated by word-level signal process-
ing that is efficiently implemented on coarse-grained reconfigurable processors. The
Montium coarse-grained reconfigurable processor is an example of such a processor,
enabling energy-efficient implementation of wireless communication receivers. This
is illustrated for three classes of receiver baseband processing: UMTS Rake receivers,
OFDM baseband processing (HiperLAN/2), and digital broadcasting receivers (DAB,
DRM, and DVB). Furthermore, an MP-SoC, containing multiple Montiums, is a suit-
able platform for the implementation of cognitive radio (CR). The flexibility offered by
coarse-grained reconfigurable processors supports the efficient implementation of new
communication paradigms.
Because of the large number of transistors envisaged on future integrated circuits, a
processing platform will not be fixed during its lifetime due to faults in production or
wear. Furthermore, the applications are not fixed. Quality-of-service requirements and
environmental conditions change, and cognitive radio has changing requirements by
definition. Consequently, applications need to be mapped onto the processing platform
at runtime.
Realizing that wireless communication applications are streaming applications
explains the use of data flow graphs to model these applications. Data flow graphs natu-
rally fit platforms with multiple processing cores where nodes of the graph are mapped
onto the processing cores and edges are mapped onto the interconnecting network-on-
chip. The use of data flow graphs supports the runtime mapping.

References

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[2] 3rd Generation Partnership Project. 2004. Physical layer—General description.
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