Information Technology Reference
In-Depth Information
CL3 4 0
X YZ11
CL34 0 X YZ11
CL340
CS220
Figure 3.1
PC card
Clock (output). The bus CLK is set to 4.772 727 MHz (for PC bus and 8.33
MHz for ISA bus) and provides synchronisation of the data transmission (it is
derived from the OSC clock).
CLK
ALE
Address latch (output). The bus address latch indicates to the expansion bus that
the address bus and bus cycle control signals are valid. It thus indicates the be-
ginning of a bus cycle on the expansion bus.
IOR
I/O read (input/output). I/O read command signal indicates that an I/O read
cycle is in progress.
IOW
I/O write (input/output). I/O write command signal indicates that an I/O write
bus cycle is in progress.
System memory read (output). System memory read signal indicates a memory
read bus cycle for the 20-bit address bus range (0h to FFFFFh).
SMEMR
SMEMW
System memory write (output). System memory write signal indicates a mem-
ory read bus cycle from the 20-bit address bus range (0h to FFFFFh).
Bus ready (input). The bus ready signal allows a slave to lengthen the amount
of time required for a bus cycle.
IO CH RDY
PC card connections
Figure 3.2
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