Information Technology Reference
In-Depth Information
(a)
It is on the motherboard, and not located beside the processor
(b)
It is located beside the processor, and not located on the motherboard
(c)
It is faster
(d)
It is made from DRAM memory rather than SRAM
A.5.12
What happens when a cache miss occurs in the second-level cache controller:
(a)
It takes data from the nearest cached address
(b)
The cache controller makes a guess about the data
(c)
An access is made to the main DRAM memory
(d)
The addressed memory is ignored
A.5.13
Explain how the byte enable lines (BE
0
-BE
3
) are used to address one or more
bytes at a time. Outline how these lines are used with the other address lines (A
2
-
A
31
).
A.5.14
Explain the method that the 80386/80486 uses to support 8-bit, 16-bit and 32-bit
registers.
A.5.15
Outline the main cache control architectures.
A.5.16
Outline major enhancements that have occurred with the Pentium (if possible,
access the www.intel.com WWW site and determine the most up-to-date informa-
tion on the latest processors).
