Information Technology Reference
In-Depth Information
•
Deferred reply transactions stop the processor from having to wait for slow devices;
transactions that require a long time can be completed later, that is, deferred.
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Deeply pipelined bus transactions where the bus supports up to eight outstanding pipe-
lined transactions.
The Pentium III processor integrates the best features of the Pentium microarchitecture proc-
essors, such as dynamic execution performance, a multitransaction system bus, and Intel
MMX media enhancement technology. In addition, the Pentium III processor offers Stream-
ing SIMD Extensions with 70 new instructions enabling advanced imaging, 3D, streaming
audio and video, and speech recognition applications.
A.4.4 System overview
Figure A.10 outlines the main components of a Pentium system. A major upgrade is the sup-
port for up to four processors. The memory contr
ol an
d dat
a pa
th control logic provides the
memory control signals, that is, memory address,
RAS
and
CAS
signals. The data path logic
moves the data between the processor bus and the memory data bus. The memory interface
component interfaces the memory data bus with the DRAM devices. Both interleaved and
non-interleaved methods are generally supported. The memory consists of dual in line mem-
ory modules, that is, DIMMs. A DIMM module supports 64 bits of data, and eight parity or
ECC bits.
Memory
data path
and
memory
control
Processor
Memory I/F
component
Memory
Processor
PCI bridge
Processor
PCI bus
Standard
bridge
EISA/ISA
component
EISA/ISA bus
Processor
Figure A.10
Pentium architecture
The PCI bridge provides the interface between the processor bus and the PCI bus. The stan-
dard bridge provides an interface between the PCI bus and the EISA/ISA bus. The EISA/ISA
support component provides the EISA/ISA bus support functions, for example, timers, inter-
rupt control, flash ROM, keyboard interface, LA/SA translation and XD bus control.
A.5 Exercises
A.5.1
Which was one of the first 8-bit Intel processors:
