Information Technology Reference
In-Depth Information
Figure A.5 shows the main 80386/80486 processor connections. The Pentium processor con-
nections are similar but it has a 64-bit data bus. There are three main interface connections:
the memory/IO interfac
e,
interrupt interface and DMA interface.
The write/read (
W/R
) line determines whether data is written to (
W
) or read from (
R
)
memory
. P
Cs can interface directly with memory or can interface to isolated memory. Signal
line
M/IO
differentiates between the two types. If it is high then the direct memory is ad-
dressed, else if it is low then the isolated memory is accessed.
The 80386DX and 80486 have an external 32-bit data bus (D
0
-D
31
) and a 32-bit address
bus ranging from A
2
to A
31
.
T
he
tw
o lo
wer a
ddre
ss lines
, A
0
and A
1
, are decoded to produce
t
he
byte enable signals
BE0
,
B
E1
,
BE2
and
BE3
. The
BE
0
lin
e activates when A
1
A
0
is 00,
BE1
activates when A
1
A
0
is 01,
BE2
activates when A
1
A
0
,
BE3
actives when A
1
A
0
is 11. Fig-
ure A.6 illustrates this addressing.
The byte enable lines are also
used
to access 8, 16, 24 or 32 bits of data at a time. When
addressing a si
ngle
byte
, on
ly the
BE0
line will be active (D
0
-D
7
), if 16 bits of data are t
o b
e
acce
ss
ed t
hen
BE0
and
BE1
will be active (D
0
-D
15
), if 32 bits are to be accessed then
BE0
,
BE1
,
BE2
a
n
d
BE3
are active (D
0
-D
31
).
The
D/C
line differentiates between data and control signals. When it is high then data
is read from or written to memory, else if it is low then a control operation is indicated, such
as a shutdown command.
A
2
-A
31
HOLD
HLDA
BE
0
-BE
3
80386/
80486
D
0
-D
31
INTR
NMI
RESET
W/
-
R
D/
-
C
M/
-
IO
Figure A.5
Some of the 80386/80486 signal connections
The interrupt lines are interrupt request (
INTR
), nonmaskable interrupt request (
NMI
) and
system reset (
RESET
), all of which are active high signals. The
INTR
line is activated when
an external device, such as a hard disk or a serial port, wishes to communicate with the
processor. This interrupt is maskable and the processor can ignore the interrupt if it wants.
The NMI is a non-maskable interrupt and is always acted on. When it becomes active the
processor calls the nonmaskable interrupt service routine. The
RESET
signal causes a
hardware reset and is normally made active when the processor is powered up.
A.3.3 80386/80486 registers
The 80386 and 80486 are 32-bit processors and can thus operate on 32-bits at a time. It thus
has expanded 32-bit registers, which can also be used as either 16-bit or 8-bit registers. The
general purpose registers, such as AX, BX, CX, DX, SI, DI and BP have been expanded and
are named EAX, EBX, ECX, EDX, ESI, EDI and EBP, respectively, as illustrated in Figure
A.7. The CS, SS and DS registers are still 16 bits, but the flag register has been expanded to
32 bits and is named EFLAG.
