Information Technology Reference
In-Depth Information
FERR (O)
Indicates that the processor has detected an error in the internal floating-
point unit.
FLUSH (I)
When active the processor writes the complete contents of the cache to
memory.
HOLD, HLDA (I/O)
The bus hold (HOLD) and acknowledge (HLDA) are used for bus arbitra-
tion and allow other bus controllers to take control of the buses.
IGNNE (I)
When active the processor ignores any numeric errors.
INTR (I)
The interrupt request line is used by external devices to interrupt the proces-
sor.
KEN (I)
This signal stops caching of a specific address.
LOCK (O)
If active the processor will not pass control to an external bus controller,
when it receives a HOLD signal.
M/
IO
,
D/
C
,
W/
R
(O)
See Table A.2.
NMI (I)
The non- maskable interrupt signal causes an interrupt 2.
PCHK (O)
If it is set active then a data parity error has occurred.
PLOCK (O)
The active pseudolock signal identifies that the current data transfer re-
quires more than one bus cycle.
PWT, PCD (O)
The page write through (PWT) and page cache disable (PCD) are used with
cache control.
RDY
(I)
When active the addressed system has sent data on the data bus or read data
from the bus.
RESET (I)
If the reset signal is high for more than 15 clock cycles then the processor
will reset itself.
Table A.2
Control signals
Description
M/
IO
D/
C
W/
R
0
0
0
Interrupt acknowledge sequence
0
0
1
STOP/special bus cycle
0
1
0
Reading from an I/O port
0
1
1
Writing to an I/O port
1
0
0
Reading an instruction form memory
1
0
1
Reserved
1
1
0
Reading data from memory
1
1
1
Writing data to memory
