Information Technology Reference
In-Depth Information
IGN - IGNNE
FLH - FLUSH
AM - A20M
HOL - HOLF
KEN - KEN
BRD - BRDY
D/C - D/C
BRQ - BREQ
HLD - HLDA
INT - INTR
RES - RESET
RDY - RDY
BE0 - BE0
BE1 - BE1
BE2 - BE2
BE3 - BE3
M/I - M/IO
PLK - PLOCK
BLT - BLAST
AHD - AHOLD
EAD - EADS
B16 - BS16
BOF - BOFF
W/R - W/R
PCH - PCHK
ADS - ADS
D20 D19 D11 D9 GND
DP1 GND GND Vcc
GND GND GND D2
D0
A31 A28 A27
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
D22 D21 D18 D13 Vcc
D8
VCC D3
D5
Vcc
D6
Vcc
D1
A29 GND A25 A26
GND CLK D17 D10 D15 D12 DP2 D16 D14 D7
D4
DP0 A30 A17 Vcc
A23
D23 GND Vcc A19 GND
DP3 GND Vcc A21 A18 A14
D24 D25 D27 A24 Vcc GND
GND Vcc D26 A22 A15 A12
D29 D31 D28 A20 Vcc GND
GND Vcc D30 A16 Vcc GND
A13 Vcc GND
GND Vcc A9 Vcc GND
A5 A11 GND
A7 A8 A10
A2 Vcc GND
IGN NMI FLH BRQ A3 A6
INT RES BS8 GND RDY Vcc Vcc BE1 Vcc Vcc Vcc M/I Vcc PLK BLT A4
AHD EAD B16 BOF GND BE3 GND GND PCD GND GND GND W/R GND PCH
486DX
PGA
AM
HOL KEN
BRD BE2 BE0 PWT D/C LCK HLD
ADS
ABCDEF GHJ KL MNPQRS
Figure A.4
i486DX processor
AHOLD (I)
When active a different bus controller can access have access to the address
bus. This is typically used in a multi-processor system.
BE0 - BE3 (O)
The byte enable lines indicates which of the bytes of the 32-bit data bus are
active.
BLAST (O)
Indicates that the current burst cycle will end after the next BRDY signal.
BOFF (I)
The backoff signal informs the processor to deactivate the bus on the next
clock cycle.
BRDY (I)
The burst ready signal is used by an addressed system has sent data on the
data bus or read data from the bus.
BREQ (O)
Indicates that the processor has internally requested the bus.
BS16 , BS8 (I)
The BS16 signal indicates that a 16-bit data bus is used, the BS8 signal
indicates that a 8-bit data bus is used. If both are high then a 32-bit data is
used.
DP0-DP3 (I/O)
The data parity bits gives a parity check for each byte of the 32-bit data bus.
The parity bits are always even parity.
EADS (I)
Indicates that an external bus controller has put a valid address on the ad-
dress bus.
