PC Processors - Computer Busses - page 499

A.3 80386/80486

A.3.1 Introduction
The 32-bit 80386 processor was a great leap in processing power and for the first time many
PCs could properly run graphical user interface software (such as Microsoft Windows). A
key to its success was that it was fully compatible with the previous 8088/8086/80286 proc-
essors. The DX version has full 32-bit data and address buses and can thus address up to
4 GB of physical memory. An SX version with a stripped-down 16-bit external data bus and
24-bit address bus version can access only up to 16 MB of physical memory (at its time of
release this has a large amount of memory).
The 80486DX basically consists of an improved 80386 with a memory cache and math
co-processor integrated onto the chip. An SX version had the link to the math co-processor
broken. At the time a limiting factor was the speed of the system clock (which was limited to
around 25 MHz or 33 MHz). Thus clock doublers, treblers or quadrupers allows the proces-
sor to multiply the system clock frequency to a high speed. Thus internal operations within
the processor could be carried out at much higher speeds. Then accesses the external devices
would slow down to the system clock. As most of the operations within the computer involve
the processor then the overall speed of the computer is improved (roughly by about 75% for
a clock doubler). 80486 processors were also released. In these devices the processor runs at
a higher speed than the system clock. Typically, systems with clock doubler processors are
around 75% faster than the comparable non-doubled processors.

A.3.2 80486 pin out
To allow for easy upgrades and to save space the 80486 and Pentium processors are available
in pin-grid array (PGA) form. The 80486DX processor is available as a 168 pin PGA, as
illustrated in Figure A.4. The PGA chip is inserted into a zero-insertion force (ZIF) socket on
the motherboard of the PC.
It can be seen that the 486 processor has a 32-bit address bus (A0-A31) and a 32-bit data
bus (D0-D31). The pin definitions are defined in Table A.2.
Table A.3 defines the how t he c o ntrol signals are interpreted. For the STOP/special bus cy-
cle, the byte enable signals ( BE0 - BE3 ) are used to further define the cycle. These are:

• Write-back cycle BE0 =1, BE1 =1, BE2 =1 , BE3 =0.

• Halt cycle BE0 =1, BE1 =1, BE2 =0 , BE3 =1.

• Flush cycle BE0 =1, BE1 =0, BE2 =1 , BE3 =1.

• Shut-down cycle BE0 =0, BE1 =1, BE2 =1 , BE3 =1.

The 486 integrates a processor, cache and a math co-processor onto a single IC, its pin con-
nections are:

A2-A31 (I/O) The 30 most significant bits of the address bus.

A20M (I) When active low, the processor internally masks the address bit A20 before

every memory access.

ADS (O) Indicates that the processor has valid control signals and a valid address

signals.