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21.6 Bit timing
Each bit on the CAN bus is, for timing purposes, divided into at least 4 quanta . The quanta
are logically divided into four groups or segments :
Synchronisation segment - this is one quantum long and is used for synchronisation of
the clocks. A bit edge is expected to take place here when the data changes on the bus.
Propagation segment - this is required to compensate for the delay in the bus lines.
Phase segment 1 - this may be shortened (Phase segment 1) or lengthened (Phase seg-
ment 2), if necessary, to keep the clocks in synchronisation. The bus levels are sampled
at the border between Phase segment 1 and Phase segment 2.
Phase segment 2.
Figure 21.4 shows a schematic of the bit. Most CAN controllers also provide an option to
sample three times during a bit. In this case, the sampling occurs on the borders of the two
quanta that precedes the sampling point, and the result is subject to majority decoding.
One bit
Prop-seg
Phase 1
Phase 2
Sync
Sampling point
Figure 21.4
Bit timing
21.6.1 Clock synchronisation
In order to adjust the on-chip bus clock, a CAN controller can either shorten or lengthen a bit
by a whole number of quanta. The maximum number of quanta is defined as the
synchronisation jump width:
Hard synchronisation - occurs on the recessive-to-dominant transition of the start bit.
The bit time is restarted from that edge.
Resynchronisation - occurs when a bit edge does not occur within the synchronisation
segment in a message. For this one of the phase segments is shortened or lengthened
with an amount that depends on the phase error in the signal (the maximum value is de-
fined by the synchronisation jump width).
21.6.2 Bus failure modes
The ISO 11898 standard defines several fault modes on a CAN bus cable, these are:
1. CAN_H interrupted.
2. CAN_L interrupted.
3. CAN_H shorted to battery voltage.
 
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