Information Technology Reference
In-Depth Information
1. Data read and write cycles - These involve transfers between the host and the peripheral.
2. Address read and write cycles - These pass address, channel, or command and control
information.
Table 17.3 defines the names of the signal in the nibble mode. The
WRITE
occurs automati-
cally when the host writes data to the output lines.
The data write cycle has the following sequence:
1. Program executes an I/O write cycle to the base address port + 4 (EPP data port), see Ta-
ble 1
7.4. Th
en the following occur with hardware:
2. The
WRITE
line is set LOW, which puts the data on the data bus.
3. The
DATASTB
is then set LOW.
4. The host waits for peripheral to set the
WAIT
line HIGH.
5. The
DATASTB
and
WRITE
are then HIGH and the cycle ends.
The important parameter is that it takes just one memory-mapped I/O operation to transfer
data. This gives transfer rates of up to 2 million bytes per second. Although it is not as fast as
a peripheral transferring over the ISA, it has the advantage that the peripheral can transfer
data at a rate that is determined by the peripheral.
Table 17.3
EPP mode signals
Compatibility
signal na
me
EPP mode
name
In/out
Description
Out
A LOW for a write operation while a HIGH indi-
cates a read operation.
STROBE
WRITE
Out
Indicates a data read or write operation.
AUTO
FEED
DATASTB
Out
Indicates an address read or write operation.
SELECT
INPUT
ADDRSTROBE
Out
Peripheral reset when LOW.
INIT
RESET
In
Peripheral sets this line LOW when it wishes to
interrupt to the host.
ACK
INTR
BUSY
In
When it is set LOW it indicates that it is valid to
start a cycle, else if it is HIGH then it is valid to end
the cycle.
WAIT
PE
User defined
In
Can be set by each peripheral.
SELECT
User defined
In
Can be set by each peripheral.
User defined
In
Can be set by each peripheral.
ERROR
D0-D7
AD0-AD7
In/out
Bidirectional address and data lines.
