AGP - Computer Busses - page 203

The maste r uses two clock periods to transfer the entire address using AD[31:0] and
0] C/BE[3 . Within the first clock period, the master provides the lower address bits (A31-

A03) and the length encoding on (A2-A0), as with a 32-bit request, but uses the 1101 com-
mand (DAC) encoding on

:

C/BE[3 instead of the actual command. The second clock of
the request co ntains the upper address bits (A63-A32) on AD[31:0] and the actual command
on

: 0]

. C/BE[3 : 0]

11.7 Addressing modes and bus operations

AGP transactions differ from PCI transactions in several ways:

• In AGP, pipelined read/write transactions are disconnected from their associated access
request, where the request and associated data may be separated by other AGP opera-
tions. Conversely, a PCI data phase is connected to its associated address phase, with no
interventions allowed. This helps to maintain the pipe depth and allows the core logic to
ensure a sufficiently large buffer for receiving the write data, before locking up the bus
on a data transfer that could be blocked awaiting buffer space. The rules for the order of
accesses on the AGP bus are not based on the order of the data transfer, but on the arrival
order of access requests.
• AGP has different bus commands which allow access only to the main system memory.
PCI allows access to multiple address spaces: memory, I/O and configuration.
• In AGP, memory addresses are always aligned in 8-byte references, whereas PCI uses 4-
byte, or lower, references (the number of bytes addressed is defined with the

C/BE[3 ).
The reason for the increased AGP addressing granularity (from four in the PCI bus to
eight in AGP) is because modern processors use a 64-bit data bus and can manipulate 64
bits at a time. The memory systems are also 64 bits wide.
• In AGP, pipelined access requests have an exp licitly d efined access length or size. In PCI
transfer lengths are defined by the duration of FRAME .

: 0]

11.8 Register description

The PCI bridge supports AGP through two sets of registers, which are accessed via I/O ad-
dresses. These are:

• Configuration address (CONFADD) - Enables/disables the configuration space and de-
termines what portion of configuration space is visible through the configuration data
window.
• Configuration data (CONFDATA) - 32-bit/16-bit/8-bit read/write window into configu-
ration space.