Information Technology Reference
In-Depth Information
•
The IDSEL signal is asserted. As the AGP connector does not support IDSEL then it is
connected to AD16. This is done by connecting it internally for AGP operation, but ex-
ternally for PCI operation.
Initially the AGP device asserts
DEVSEL
when the bus command is configuration (read or
write). AD16 is set to a '1' and AD1 and AD0 are '00'. These cause the device's configura-
tion space to be accessed. The system software then scans all configuration spaces by assert-
ing different AD signals between AD16 and AD31, and using PCI configuration read or
write commands.
11.6 Bus commands
The AGP bus uses the command lines (
C/BE[3
:
0]
) to indicate the type of pipelined transac-
tion on the AD bus or SBA port. These are:
0000
Read - Starting at the specified address, read
n
sequential Qwords, where
n
= (length_field + 1). The length_field is provided by the lower three bits on
the AD bus (A2-A0).
0001
Read (hi-priority). As 'Read', but the request is queued in the high priority
queue. The reply data may be returned out of order with respect to other
requests.
0010
Reserved.
0011
Reserved.
0100
Write - Startin
g at the s
pecified address, write
n
sequential Qwords, as
enabled by the
, where
n
= (length_field + 1).
C/BE[3
:
0]
0101
Write (hi-priority) - As 'Write', but indicates that the write data must be
transferred from the master within the maximum latency window estab-
lished for high priority accesses.
0110
Reserved.
0111
Reserved.
×
1000
Long read - As 'Read',
except for access size, in this case,
n
= 4
(length_field + 1) allowing up to 256 byte transfers.
1001
Long read (hi-priority) - As 'Read (hi-priority)'
except for access size
which is the same as for 'Long Read'.
1010
Flush - Similar to 'Read'. Forces all low-priority write accesses ahead of it
to the point that all the results are fully visible to all other system agents.
1011
Reserved.
1100
Fence - Creates a boundary in a single master's low-priority access stream
around which writes may not pass reads.
1101
Dual address cycle (DAC) - used by the master to transfer a 64-bit address
to the core logic when using the AD bus.
1110
Reserved.
1111
Reserved.
.
