Information Technology Reference
In-Depth Information
The signal lines split into four main groups:
•
AGP requests.
•
AGP flow control.
•
AGP status.
•
AGP clocking.
Also,
the P
CI lin
es are
identified with a preceding G, such as GAD[31:0] for the PCI AD
bus,
GSTOP
for
STOP
, and so on.
11.4.1 Requests
AGP supports two methods of queuing requests by an AGP master. A master selects the re-
quired
metho
d during start-up and is not allowed to change when set up. The methods either
use the
PIPE
signal line or they use the SBA port. These signals cannot be used at the same
time. These lines are defined as:
PIPE
On the master (the graphics controller),
PIPE
is a sustained tristate signal
and is an input to the target (the core logic). When assessed by the current
master it indicates a pipelined request, so that the full width request is to be
queued by t
he ta
rget. The master queues one request each rising edge of
CLK while
PIPE
is asserted.
SBA[7:0]
These signals are outputs from the master and are inputs to the target, and
they indicate the sideband address (SBA) port which gives an additional
bus to pass requests (address and command) to the target from the master.
11.4.2 Flow control
Apart from the normal PCI flow control lines, the following have been added to AGP:
RBF
The read buffer full (RBF) signal indicates that the master is ready to ac-
cept previously requested low priority (LP) read data or not. When it is ac-
tive (LOW), the arbiter is not allowed to initiate the return of low priority
read data to the master. It is made inactive by either the AGP target or
motherboard.
WBF
The write buffer full (WBF) signal indicates that the master is ready to ac-
cept fast write (FW) data. When it is active (LOW), the core logic arbiter is
not allowed to initiate a transaction to provide FW data. It is made inactive
by either the AGP target or motherboard.
11.4.3 Status signals
The AGP status signals indicate how the AD bus is used in future transactions, such as using
it to queue new requests, return previously requested read data, or send previously queued
write data. These lines are always an output from the corelogic and an input to the master,
and are:
ST[2:0]
These provide information from the arbiter to the master on the mode of
