Information Technology Reference
In-Depth Information
8.3.1 Window enable register
The window enable register has a register index of 06h (and 46h for the second socket). The
definition of the register is
Bit 7
IOW1 I/O window 1 enable (1)/ disable (0).
Bit 6
IOW0 I/O window
0 enable
(1)/ disable (0).
Bit 5
DEC
If active (1)
MEMCS16
generated from A23-A12, else from A23-A17.
Bit 4
MW4
Memory window 4 enable (1)/ disable (0).
Bit 3
MW3 Memory window 3 enable (1)/ disable (0).
Bit 2
MW2 Memory window 2 enable (1)/ disable (0).
Bit 1
MW1 Memory window 1 enable (1)/ disable (0).
Bit 0
MW0 Memory window 0 enable (1)/ disable (0).
8.3.2 FIRST set up for memory window
The FIRST window memory address is made up of a low byte and a high byte. The format of
the high-byte register is
Bit 7
DS
Data bus size: 16-bit (1)/ 8-bit (0).
Bit 6
0WS
Zero wait states: no wait states (1)/ additional wait states (0).
Bit 5
SCR1
Scratch bit (not used).
Bit 4
SCR0
Scratch bit (not used).
Bit 3-0
Window start address A23-A20.
The format of the low-byte register is
Bit 7-0 A19-A12.Window start address A19-A12.
8.3.3 LAST set up for memory window
The LAST window memory address is made up of a low byte and a high byte. The format of
the high-byte register is
Bit 7, 6
WS1, WS0
Wait state.
Bit 5, 4
Reserved.
Bit 3-0
A23-A20
Window start address A23-A20.
The format of the low-byte register is
Bit 7-0
Window start address A19-A12.
8.3.4 Card offset set up for memory window
The card offset memory address is made up of a low byte and a high byte. The format of the
high-byte register is
Bit 7
WP
Write protection: protected (1)/ unprotected (0).
Bit 6
REG
REGISTER SELECT
enabled. If set to a 1 then access to attribute
memory, else common memory.
Bit 5-0
Window start address A25-A20.
