Information Technology Reference
In-Depth Information
•
Check for active.
•
Read multiple sectors.
•
Write multiple sectors.
•
Lock drive door.
The control of the disk is achieved by passing a number of high-level commands through a
number of I/O port registers. Table 6.3 outlined the pin connections for the IDE connector.
Typically pin 20 is missing on the connector cable so that it cannot be inserted the wrong
way, although most systems buffer the signals so that the bus will not be damaged if the ca-
ble is inserted the wrong way. The five control signals which are unique to the IDE interface
(and not the AT bus) are
•
CS3FX
,
CS1FX
-
these are used to identify either the master or the slave.
•
PDIAG
(passed diagnostic) - used by the slave drive to indicate that it has passed its di-
agnostic test.
•
SP / DA
(slave present/drive active) - used by the slave drive to indicate that it is present
and active.
The other signals are
•
IOCHRDY
- This signal is optional and is used by the drive to tell the processor that it re-
quires extra clock cycles for the current I/O transfer. A high level informs the processor
that it is ready, while a low informs it that it needs more time.
•
DRQ3
,
DACK3
- These are used for DMA transfers.
6.8.1 AT task file
The processor communicates with the IDE controller through data and control registers (typi-
cally known as the AT task file). The base registers used are between 1F0h and 1F7h for the
primary disk (170h and 177h for secondary), and 3F6h (376h for secondary), as shown in
Figure 6.4. Their function is:
Port
Function
Bits
Direction
1F0h Data register
16
R/W
1F1h
Error register
8
R
Precompensation
8
W
1F2h
Sector count
8
R/W
1F3h
Sector number
8
R/W
1F4h
Cylinder LSB
8
R/W
1F5h
Cylinder MSB
8
R/W
1F5h
Drive/head
8
R/W
1F6h
Status register
8
R
Command register
8
W
3F6h
Alternative status register
8
R
Digital output register
8
W
3F7h
Drive address
8
R
