Information Technology Reference
In-Depth Information
Bit
Description
7:6
Reserved.
5
Defines if DRAM cache is present - 1 (present), 0 (not present).
4:0
DRAM cache refresh timer value.
5.2.6 Power management
The PIIX4 has enhanced power management over the PIIX3 and can detect when a specific
device is idle. The system management software is then informed, which then can place the
idle device into a power managed condition (such as local stand by o r powered off). Accesses
targeted to that device are then monitored. When detected, an SMI is generated to allow the
software to restore the device to operation.
The PIIX4 supports the Advanced Configuration and Power Interface (ACPI) specifica-
tion. The software consists of system management mode (SMM) BIOS for legacy control
and operating system for ACPI. The basic operation consists of software setting up the de-
sired configurations and power management mode and corresponding power saving levels.
The hardware then performs the necessary actions to maintain the power mode. The I/O chip
also monitors the system for events which may require changing the system power mode.
5.3
Exercises
5.3.1
The data bus signals which connect to the processor are:
(a)
HD0-HD63
(b)
D0-D63
(c)
HA0-HA63
(d)
AD0-AD63
5.3.2
Which device provides the bridge between the processor, second-level cache,
DRAM and the PCI bus:
(a)
PIIX3/4
(b)
HXC
(c)
RFC/MRFC
(d)
TXC/MTXC
5.3.3
Which device provides the bridge between the PCI bus and other busses, such as
the IDE, ISA and USB:
(a)
PIIX3/4
(b)
HXC
(c)
RFC
(d)
TXC
5.3.4
The maximum achievable data throughput for a 33 MHz, 32-bit PCI is 132 MB/s.
Why is this not achievable in the normal multiplexed mode:
(a)
Half of the bus is used for addresses, the other half for data
(b)
The bus must slow down because of synchronisation problems
(c)
The address and data line are shared (multiplexed address then data).
(d)
The clock rate is halved for all transfers
5.3.5
How does a cache identify the address of the data it has in its memory:
(a)
The full address is stored along with the data
(b)
It is tagged (CTAG).
 
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