Information Technology Reference
In-Depth Information
5.1.5 DRAM interface
The DRAM interface supports from 4 MB to 512 MB with eight RAS lines (RAS0-RAS7)
and a 64-bit data path with eight parity bits. It can use either a 3.3 V or a 5 V power supply
and both standard page mode and extended data out (EDO) memory are supported with a
mixture of memory sizes for 1 MB, 2 MB and 4 MB-deep SIMMs and symmetrical address-
ing for 16 MB-deep SIMMs.
Each SIMM (single in-line memory module) has 12 input address lines and has a 32-bit
data output. They are normally available with 72 pins (named tabs) on each side. These pins
can read the same signal because they are shorted together on the board. For example, tab 1
(pin 1) on side A is shorted to tab 1 on side B. Thus, the 144 tabs only gives 72 useable sig-
nal connections.
Figure 5.5 shows how the DRAM memory is organized. It shows bank 1 and 2 (and does
not show banks 3 and 4). Each bank has two modules, such as modules 0 and 1 are in bank 0.
The bank is selected with the MRAS lines, for example bank 1 is selected with MRAS0 and
MRAS1, bank 1 by MRAS2 and MRAS3, and so on. An even-numbered module gives the
lower 32 bits (MD0-MD31) and the odd number modules give the upper 32 bits (MD32-
MD63). Each module also provides four parity bits (MP0-MP3 and MP4-MP7).
DIMMs (dual in-line memory modules) have independent signal lines on each side of the
module and are available with 72 (36 tabs on each side), 88 (44 tabs on each side), 144 (72
tabs on each side), 168 (84 tabs on each side) or 200 tabs (100 tabs on each side). They give
greater reliability and density and are used in modern high performance PC servers.
MRAS0
MRAS1
MRAS0
MRAS1
-RAS0
-RAS1
-RAS2
-RAS3
-CAS0
-CAS1
-CAS2
-CAS3
MRAS2
MRAS3
MRAS2
MRAS3
-RAS0
-RAS1
-RAS2
-RAS3
-CAS0
-CAS1
-CAS2
-CAS3
MCAS0
MCAS1
MCAS2
MCAS3
MCAS0
MCAS1
MCAS2
MCAS3
MWE
-W
MWE
-W
MD0-MD31
MD0-MD31
Module 0
MP0-P3
Module 2
MP0-P3
MA0-MA11
MA0-MA11
MRAS0
MRAS1
MRAS0
MRAS2
-RAS0
-RAS1
-RAS2
-RAS3
-CAS0
-CAS1
-CAS2
-CAS3
MRAS2
MRAS3
MRAS2
MRAS3
-RAS0
-RAS1
-RAS2
-RAS3
-CAS0
-CAS1
-CAS2
-CAS3
MCAS4
MCAS5
MCAS6
MCAS7
MCAS4
MCAS5
MCAS6
MCAS7
MWE
-W
MWE
-W
MD32-MD63
MD32-MD63
MA0-MA11
Module 1
MA0-MA11
Module 2
MP4-P7
MP4-P7
Bank 1
Bank 2
Figure 5.5
DRAM memory interface
