Motherboard Design - Computer Busses - page 122

Cache Memory Parity Address

Lines Tag

Signal Pin Signal Pin Signal Pin Signal Pin

CTAG0 207 MP0 133 MD32 74

CTAG1 260 MP1 123 MD33 75

CTAG2 261 MP2 146 MA2 317 MD34 76

CTAG3 281 MP3 113 MA3 297 MD35 76

CTAG4 238 MP4 132 MA4 277 MD36 76

CTAG5 282 MP5 124 MA5 257 MD37 76

CTAG6 302 MP6 134 MA6 237 MD38 76

CTAG7 322 MP7 122 MA7 298 MD39 76

CTAG8 303 MA8 258

CTAG9 323 MA9 319

CTAG10 324 MA10 318

MA11 278

Cache address lines
MRASR0# 121 MCASR0# 145 MAA0 300

MRASR1# 110 MCASR1# 159 MAA1 300

MRASR2# 109 MCASR2# 131 MAB0 300

MRASR3# 96 MCASR3# 173 MAB1 300

MCASR4# 130

MCASR5# 144

MCASR6# 120

MCASR7# 172

Cache control lines
CBWE# 321 COE# 259 CCS# 300 CADS# 299

CGWE# 320 CADV# 279

5.1.4 82091AA (AIP)
The AIP device integrates the serial ports, parallel ports and floppy disk interfaces. Figure
5.3 shows its connections and Figure 5.4 shows the interconnection between the AIP and the
PIIX3 device. The OSC frequency is set to 14.218 18 MHz. It can be seen that the range of
interrupts for the serial, parallel and floppy disk drive is IRQ3, IRQ4, IRQ5, IRQ6 and IRQ7.
Normally the settings are:

• IRQ3 - secondary serial port (COM2/COM4).

• IRQ4 - primary serial port (COM1/COM3).

• IRQ6 - floppy disk controller.

• IRQ7 - parallel port (LPT1).

Figure 5.4 shows the main connections between the TXC, PIIX3 and the AIP. It can be seen
that the AIP uses many of the ISA connections (such as 0WS#, IOCHRDY, and so on). The
interface between the TCX and the PIIX3 defines the PCI bus and the interface between the
PIIX3 and AIP defines some of the ISA signals.