Information Technology Reference
In-Depth Information
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Incorporates 82C54 timer for system timer, refresh request and speaker output tone.
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Non-maskable interrupts (NMI).
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PCI clock speed of 25/33 MHz. Motherboard configurable clock speed (normally
33 MHz).
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Plug-and-play support with one steerable interrupt line and one programmable chip se-
lect. The motherboard interrupt MIRQ0 can be steered to any one of 11 interrupts (IRQ3-
IRQ7, IRQ9-IRQ12, IRQ14 and IRQ15).
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Steerable PCI interrupts for PCI device plug-and-play. The PCI interrupt lines (PIRQA-
PIRQD) can be steered to one of 11 interrupt (IRQ3-IRQ7, IRQ9-IRQ12, IRQ14 and
IRQ15).
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Support for PS/2-type mouse and serial port mouse. IRQ12/M can be enabled for the
PS/2-type mouse or disable for a serial port mouse.
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Support for five ISA slots. Typical applications for ISA include 10M bps Ethernet adaptor
cards, serial/parallel port cards, sound cards, and so on.
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System power management. Allows the system to operate in a low power state without
being powered down. This can be triggered either by a software, hardware or external
event.
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Math coprocessor error function. The FERR# line goes active (LOW) when a math co-
processor error occurs. The PIIX3 device automatically generates an IRQ13 interrupt and
sets the INTR line to the processor. The PXII3 device then sets the IGNNE# active and
INTR inactive when there is a write to address F0h.
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Two 82C59 controllers with 14 interrupts. The interrupts lines IRQ1, IRQ3-IRQ15 are
available (IRQ0 is used by the system time and IRQ2 by the cascaded interrupt line).
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Universal serial bus with root hub and two USB ports. With the USB the host controller
transfers data between the system memory and USB devices. This is achieved by process-
ing data structures set up to by the host software and generated the transaction on USB.
The address lines (AD0-AD22) connect to the TXC IC and the available interrupt lines at
IRQ1, IRQ2-IRQ12, IRQ14 and IRQ15 (IRQ0 is generated by the system timer and IRQ2 is
the cascaded interrupt line). The PS/2-type mouse uses the IRQ12/M line.
5.1.3 82438 System Controller (TXC)
The 324-pin TXC BGA (ball grid array) provides an interface between the processor, DRAM
and the external buses (such as the PCI, ISA, and so on). Table 5.2 outlines its main pin con-
nections. The TXC's functionality includes:
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Supports 50 MHz, 60 MHz and 66 MHz host bus.
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Integrated DRAM controller. Supports four CAS lines and eight RAS lines. The memory
supports symmetrical and asymmetrical addressing for 1 MB, 2 MB and 4 MB-deep
SIMMs and symmetrical addressing for 16 MB-deep SIMMs.
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Integrated second level cache controller. Supports up to 512 MB of second-level cache
with synchronous pipelined burst SRAM.
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Dual processor support.
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Optional parity.
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Optional error checking and correction on DRAM. The ECC mode is software configur-
able and allows for single bit error correction and multibit error detection on single nib-
bles in DRAM.
