Information Technology Reference
In-Depth Information
4.7.2
Which I/O register address is used to access PCI configuration address space:
(a)
1F8h
(b)
CF8h
(c)
3F8h
(d)
2F8h
4.7.3
Which I/O register address is used read and write to registers in the PCI configura-
tion address space:
(a)
1FCh
(b)
CFCh
(c)
3FCh
(d)
1FCh
4.7.4
How many bits can be accessed, at a time, with the configuration address register:
(a)
8
(b)
16
(c)
32
(d)
64
4.7.5
Which company has the manufacture ID of 8086:
(a)
Compaq
(b)
Motorola
(c)
NCR
(d)
Intel
4.7.6
Explain how PCI architecture uses bridges.
4.7.7
Outline the operation of Program 4.1 and Program 4.2. Highlight the range of ad-
dresses used. Why does Program 4.2 write the bit pattern FF000000h and not
FFFFFFFFh?
4.7.8
Explain how the 32-bit PCI bus transfers data. Prove that the maximum data rate
for a 32-bit PCI in its normal mode is only 66 MB/s. Explain the mechanism that
the PCI bus uses to increase the maximum data rate to 132 MB/s.
4.7.9
How does buffering in the PCI bridge aid the transfer of data to and from the proc-
essor.
4.7.10
Explain how the PCI bus uses the command phase to set up a peripheral.
4.7.11
How are interrupt lines used in the PCI bus. Explain how these interrupts can be
steered to the ISA bus interrupt lines.
4.7.12
Outline the concept of bus mastering and how it occurs on the PCI bus. What sig-
nal lines are used?
4.7.13
Explain how the PCI bus uses configuration addresses.
