Information Technology Reference
In-Depth Information
bus operation, where the amount of time is the latency+8 PCI clock cycles.
•
Base address register - this area of memory allows the device to be programmed with an
I/O or memory address area. It can contain a number of 32- or 64-bit addresses. The for-
mat of a memory address is
Bit 64-4
Base address.
Bit 3
PRF. Prefetching, 0 identifies not possible, 1 identifies possible.
Bit 2, 1
Type. 00 - any 32-bit address, 01 - less than 1MB, 10 - any
64-bit address and 11 - reserved.
Bit 0
0. Always set to a 0 for a memory address.
For an I/O address space it is defined as:
Bit 31-2
Base address.
Bit 1, 0
01. Always set to a 01 for an I/O address.
•
Expansion ROM base address - allows a ROM expansion to be placed at any position in
the 32-bit memory address area.
•
MaxLat, MinGNT, INT-pin, INT-line - the MinGNT and MaxLat registers are read-only
registers that define the minimum and maximum latency values. The INT-Line field is a
4-bit field that defines the interrupt line used (IRQ0-IRQ15). A value of 0 corresponds to
IRQ0 and a value of 15 corresponds to IRQ15. The PCI bridge can then redirect this in-
terrupt to the correct IRQ line. The 4-bit INT-pin defines th
e int
errupt line t
hat th
e device
is using. A value of 0 defines no interrupt line, 1 defines
INTA
, 2 defines
INTB
, and so
on.
4.6
I/O addressing
The standard PC I/O addressing ranges from 0000h to FFFFh, which gives an addressable
space of 64 KB, whereas the PCI bus can support a 32-bit or 64-bit addressable memory. The
PCI device can be configured using one of two mechanisms.
Configuration mechanism 1
Passing two 32-bit values to two standard addresses configures the PCI bus:
Address
Name
Description
0CF8h
Configuration
address
Used to access the configuration address area.
0CFCh
Configuration data
Used to read or write a 32-bit (double word) value to the
configuration memory of the PCI device.
The format of the configuration address register is
Bit 31
ECD (
Enable CONFIG_DATA
) bit. A 1 activates the
CONFIG_DATA
register, while
a 0 disables it.