Information Technology Reference
In-Depth Information
4.2
PCI operation
The PCI bus cleverly saves lines by multiplexing the address and data lines. It has two modes
(Figure 4.2):
Multiplexed mode - the address and data lines are used alternately. First, the address is
sent, followed by a data read or write. Unfortunately, this requires two or three clock cy-
cles for a single transfer (either an address followed by a read or write cycle, or an ad-
dress followed by read and write cycle). This causes a maximum data write transfer rate
of 66 MB/s (address then write) and a read transfer rate of 44 MB/s (address, write then
read), for a 32-bit data bus width.
Burst mode - the multiplexed mode obviously slows down the maximum transfer rate.
Additionally, it can be operated in burst mode, where a single address can be initially
sent, followed by implicitly addressed data. Thus, if a large amount of sequentially ad-
dressed memory is transferred then the data rate approach the maximum transfer of
133 MB/s for a 32-bit data bus and 266 MB/s for a 64-bit data bus.
If the data from the processor is sequentially addressed data then PCI bridge buffers the in-
coming data and then releases it to the PCI bus in burst mode. The PCI bridge may also use
burst mode when there are gaps in the addressed data and use a handshaking line to identify
that no data is transferred for the implied address. For example in Figure 4.2 the burst mode
could involve Address+1, Address+2 and Address+3 and Address+5, then the byte enable
signal can be made inactive for the fourth data transfer cycle.
Address3
Data3
Address1
Data1
Address2
Data2
Address3
Data
PCI bus
(normal mode)
Address1
Data1
Data2
Address2
Address
Data1
Data2
Data3
Data4
Data5
Data1
Data2
Data3
Data4
Data5
Address
PCI bus
(burst mode)
Figure 4.2
PCI bus transfer modes
To accommodate the burst mode, the PCI bridge has a prefetch and posting buffer on both
the host bus and the PCI bus sides. This allows the bridge to build the data access up into
burst accesses. For example, the processor typically transfers data to the graphics card with
sequential accessing. The bridge can detect this and buffer the transfer. It will then transfer
 
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