Civil Engineering Reference
In-Depth Information
− Write a '1' to the SLEEP bit in the MSR and '0' to the LBACK bit in the MSR
to choose sleep mode.
− Write '0's to the LBACK and SLEEP bits in the MSR to choose normal mode.
2. Configure the Transfer Layer Configuration Registers
− Program the Baud Rate Priscilla Register and the BTR to correspond to the
network timing parameters and the network characteristics of the system.
3. Configure the AFRs
The number of AFMR and AFIR pairs that are used is chosen at build time. To con-
figure these registers, the following steps should be taken:
• Write a '0' to the UAF bit in the AFR register corresponding to the AFMR and
AFIR pair to be configured.
• Wait till the ACFBSY bit in the Status Register (SR) is '0'.
• Write the appropriate mask information to the AFMR.
• Write the appropriate ID information to the AFIR.
• Write a '1' to the UAF bit corresponding to the AFMR and AFIR pair.
• Repeat the steps mentioned above for each AFMR and AFIR pair.
4. Write to the Interrupt Enable Register (IER) to choose the bits in the Interrupt
Status Register (ISR) that can generate an interrupt.
5. Enable the CAN controller by writing a '1' to the CEN bit in the Software Reset
Register (SRR).
3.5.5.2
Transmitting a Message
A message to be transmitted can be written to either the TX FIFO or the TX HPB. A
message in the TX HPB gets priority over the messages in the TX FIFO. The TXOK
bit in the ISR is set after the CAN core successfully transmits a message.
1. Writing a Message to the TX FIFO
− Poll the TXFLL bit in the SR. The message can be written into the TX FIFO
when the TXFLL bit is '0'.
− Write the ID of the message to the TX FIFO ID memory location
(C_BASEADDR + 0 × 030).
− Write the DLC of the message to the TX FIFO DLC memory location
(C_BASEADDR + 0 × 034).
− Write the Data Word 1 of the message to the TX FIFO DW1 memory location
(C_BASEADDR + 0 × 038).
− Write the Data Word 2 of the message to the TX FIFO DW2 memory location
(C_BASEADDR + 0 × 03C).
Messages can be continuously written to the TX FIFO until the TX FIFO is full.
When the TX FIFO is full, the TXFLL bit in the ISR and the TXFLL bit in the SR
are set. If polling, the TXFLL bit in the SR should be polled after each write. If us-
